suspend-to-ram support for i.MX6Solo running yocto dora 3.10.9 BSP

[scottwarner]

This is a custom board using a i.MXSolo TO1.1 that used the Sabresd as a reference, I can run:

/ # echo mem > /sys/power/state

To enter the suspend to ram state on the reference board, however trying this on the custom board results in:

/ # echo mem > /sys/power/state

sh: write error: No such device

This worked fine on the custom board running 3.0.35, the kernel seems to be configured correctly to support power management.  Any ideas what I might be missing to enable this?

Thanks

[OtavioSalvador]

It'd be good if you update your kernel to current 3.10.17-1.0.1 BSP as it had several fixes which also include PM domain. It may, or not, fix your issue but it is a more solid foundation for work.

[vivekkaushik]

Dear Yongcai,

Being got busy in other important work and following vacations, I missed to updated you on this.

The good news is I got it working on 3.0.35 kernel, with changes done for my particular DDR3 taking help from your above inputs.

Thanks and Regards

Vivek

[scottwarner]

One other thing I noticed when I ran cat /sys/power/state to see what was supported it only showed freeze, I expected freeze standby mem, which is what I see on the reference board.

[AnsonHuang]

Hi, Scott

     I think maybe the pm init fail, so the mem mode suspend would not supported, can you check the kernel log to see whether there is failure in arch/arm/mach-imx/pm-imx6.c's imx6_pm_init function? Maybe the ocram allocation is failed.

[scottwarner]

Hi Yongcai,

That was the problem the driver wasn't loading. 

I'm not having any luck waking though, I was able use a led on the board to test that it runs to the wfi instruction in the imx6_suspend function in suspend-imx6.S.  So it seems to go to sleep fine, I just can't get it to wake.  I tried using the rtc (echo +3 > /sys/class/rtc/rtc0/wakealarm) the keyboard (echo enabled > /sys/class/tty/ttymxc0/power/wakeup) and by unmasking two other wakeup sources on our board.  I tried the rtc and keyboard on the reference board and that didn't wake up either.  Are there any know issues waking up?  I'm using an older alpha release.

Thanks

[AnsonHuang]

Hi, Scott

     We did NOT have any issue about suspend/resume, so you may need to do some debug, my suggestion is that, you can try below steps:

1. Add "no_console_suspend" into kernel command line;

2. enable UART wakeup by ""echo enabled > /sys/class/tty/ttymxc0/power/wakeup" if your board's console is ttymxc0, then echo mem > /sys/power/state" to make system enter suspend, then measure PMIC_VSTBY_REQ pin on your board, see whether this signal is high, high means system is in STOP mode;

3. Click keyboard to wakeup system, if system not resume, measure PMIC_VSTBY_REQ, it should be low, now.

4. If upper flow are OK but system still not resume, I would suggest you try pm_test:

   1). echo core > /sys/power/pm_test;

   2). echo mem > /sys/power/state;

   3) system should resume automatically after 5 seconds, if not, then there is something wrong in devices drivers.

[scottwarner]

Hi Yongcai,

Finally got to the bottom of it, our board uses a single bank of lpddr2, the problem was in suspend-imx6.S where the ddr pins are being high z'd after ddr is put in self-refresh mode, this was disabling the pull-up that was required for lpddr2 on the DQS pins (DRAM_SDQS0 - 7), so when the board woke memory wasn't functioning correctly.  If those pins are left alone in the imx6dl_ddr_io_set_lpm macro the board woke fine.

Thanks for the tip on PMIC_VSTBY_REQ, monitoring that pin showed that the cpu entered the STOP mode, then on uart activity exited STOP mode, which pointed to a memory problem.

Thanks,

Scott

[vivekkaushik]

Dear Yongcai,

I am facing the resume issue on my custom board with imx6 SoloLite. I have below observations related to my board:

1. pm_test suggested by you above is working on my board i.e. board is resuming after 5 seconds

2. but if I suspend system using below commands, my system is not resuming even if press key on console

     a). echo enabled > /sys/devices/platform/imx-uart.0/tty/ttymxc0/power/wakeup

     b). echo mem > /sys/power/state

3. please find the logs on my system below:

-----------------------------------------------------------------------

root@imx6slevk:~# echo mem > /sys/power/state

PM: Syncing filesystems ... done.

Freezing user space processes ... (elapsed 0.01 seconds) done.

Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.

add wake up source irq 104

add wake up source irq 58

add wake up source irq 36

add wake up source irq 51

PM: suspend of devices complete after 68.680 msecs

PM: late suspend of devices complete after 0.593 msecs

TES:--mx6sl_pce_st_suspend_enter--

------------------------------------------------------------------------

4. I would like to know is it mandatory to use function <mx6sl_pce_st_suspend_enter>

5. Does PMIC I2C is used in suspend/resume functionality

Many Regards

Vivek

[AnsonHuang]

Hi, Vivek

     so you were NOT able to resume from DSM, please check whether system actually go into DSM, after you echo mem to /sys/power/state, please measure PMIC_VSTBY_REQ pin on PFuse pin4, if it is high, then SOC has entered DSM. Then you press key to wake up system, if PMIC_VSTBY_REQ change to low, that means SOC exit from DSM, then if kernel did NOT resume, that means there is something wrong with SW.

     To answer your question as below:

4. What is this mx6sl_pce_st_suspend_enter for? If it blocks kernel go into DSM, you will see PMIC_VSTBY_REQ always low after you echo mem;

5. PMIC I2C should be NOT used in the late phase of suspend/resume.

[vivekkaushik]

Dear Yongcai,

Behavior of PMIC_VSTBY_REQ is same as you explained i.e high after echo mem to /sys/power/state and low when I wake up system. what can be wrong is SW now.

4. <mx6sl_pce_st_suspend_enter> was a function in board-mx6sl_evk.c which I renamed for my board as I am taking reference from Solo Lite EVK files and modifying for my board.

Also on EVK ddr used was lpddr2, and on our custom board it is 16 Bit DDR3 so do you feel this can be the issue as I am using all file of EVK in kernel for reference.

Thanks and Regards

Vivek

[AnsonHuang]

Hi, Vivek

     Yes, if your board is DDR3, two points you need to keep in mind, in arch/arm/mach-imx/anatop.c, you need to keep weak 2P5 on before suspend, it is in imx_anatop_pre_suspend function(L3.10 kernel), and also, you need to change the DDR IO setting in suspend, arch/arm/mach-imx/suspend-imx6.S, comment out imx6sl_ddr_io_set_lpm to have a try, DDR3 has different pin setting compared to LPDDR2, our BSP is for LPDDR2 by default, so you can try it first, please refer to below patch I mad on our L3.10 kernel, I am NOT sure what kernel you are using:

diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index a2795cc..f1cab13 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -77,12 +77,7 @@ static inline void imx_anatop_disconnect_high_snvs(bool enable)

void imx_anatop_pre_suspend(void)
{
-       if (cpu_is_imx6sl()) {
-               imx_anatop_enable_2p5_pulldown(true);
-               imx_anatop_disconnect_high_snvs(true);
-       } else {
-               imx_anatop_enable_weak2p5(true);
-       }
+       imx_anatop_enable_weak2p5(true);

        imx_anatop_enable_fet_odrive(true);
}
@@ -90,12 +85,7 @@ void imx_anatop_pre_suspend(void)
void imx_anatop_post_resume(void)
{
        imx_anatop_enable_fet_odrive(false);
-       if (cpu_is_imx6sl()) {
-               imx_anatop_enable_2p5_pulldown(false);
-               imx_anatop_disconnect_high_snvs(false);
-       } else {
-               imx_anatop_enable_weak2p5(false);
-       }
+       imx_anatop_enable_weak2p5(false);
}

diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index f40ae18..e0871f5 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -387,7 +387,7 @@
        .endm

        .macro  imx6sl_ddr_io_set_lpm
-
+#if 0
        mov     r10, #0
        str     r10, [r8, #0x30c] /* DRAM_DQM0 */
        str     r10, [r8, #0x310] /* DRAM_DQM1 */
@@ -414,7 +414,7 @@
        mov     r10, #0x1000
        str     r10, [r8, #0x330] /* DRAM_SDCKE0 */
        str     r10, [r8, #0x334] /* DRAM_SDCKE1 */
-
+#endif
        .endm

        .macro  imx6dl_ddr_io_save

[vivekkaushik]

Dear Yongcai,

Thanks for the value able inputs, at-least we know the problem area now. I will check on your inputs, hope it will work fine but I am also not sure and not very much comfortable in assembly language but still will try to solve it.

I am using kernel-3.0.35.

Thanks and Regards

Vivek

[vivekkaushik]

Dear Yongcai,

In Kernel 3.0.35

1. The file is mx6_suspend.S in arch/arm/mach-mx6/, I have tried commenting sl_ddr_io_set_lpm but still system is not resuming

2. For weak 2p5 enable, I am not getting where and what to modify for imx6 Solo Lite

3. Is there any thing else I have to look and change for DDR3 in mx6_suspend.S or any other file.

Thanks and Regards

Vivek

[AnsonHuang]

Hi,

    2. For weak 2p5 enable, I am not getting where and what to modify for imx6 Solo Lite

          arch/arm/mach-mx6/system.c,

202                        if (cpu_is_mx6q() || cpu_is_mx6dl() ||

203                                (cpu_is_mx6sl() && ddr_type == MX6_DDR3)) {

204                                /* If stop_mode_config is clear, then 2P5 will be off,

205                                need to enable weak 2P5, as DDR IO need 2P5 as

206                                pre-driver */

207                                if ((__raw_readl(anatop_base + HW_ANADIG_ANA_MISC0)

208                                        & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) {

209                                        /* Enable weak 2P5 linear regulator */

210                                        anatop_val = __raw_readl(anatop_base +

211                                                HW_ANADIG_REG_2P5);

212                                        anatop_val |= BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG;

213                                        __raw_writel(anatop_val, anatop_base +

214                                                HW_ANADIG_REG_2P5);

215                                }

    As far as I know, you just need to comment out the sl_ddr_io_set_lpm, and keep weak 2P5 on in arch/arm/mach-mx6/system.c, suspend/resume should be working for SL with DDR3. I found that we have supported SL+DDR3 on our internal L3.0.35 kernel, I attached the patch here, you can refer to it, hope it helps.

[vivekkaushik]

Dear Yongcai,

Thanks for providing the much needed patch, all the files got patched properly.

however I am getting patch application failure for mx6_mmdc.c, when I tried to manually apply the patch I found that your mx6_mmdc.c file is different from mine.

Can you please send me your mx6_mmdc.c file or location from where I can download the updated 3.0.35 kernel which you are referring.

Thanks and Regards

Vivek