no imx6solo ecspi1 clk in master mode

[coilnpark]

I am using ecspi1 as a master mode.

But CLK is not working. I don't know why it is not working...

I can only see the spidev0.0 in the dev/...

Currently, CLK signal is now, MOSI is high, MISO is low, SS is high..

I am using 4.1.15.2.0.1 of kernel.

&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

spidev0: spi@0 {
      compatible = "spidev";
      spi-max-frequency = <20000000>;
      reg = <0>;
};

pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x100b1
>;
};

[coilnpark]

I solved this issue. My pin setting was correct. I just didn't know how to test spi pin.

When I tested spi by this command "echo hello > /dev/spidev0.0", I could see spi signals as below.

[igorpadykov]

thanks Coiln for sharing solution.

Best regards
igor

[coilnpark]

Hi igor,

There was a problem with SS pin.

As you knew, in the community, everybody said we should use gpio pin as a SS pin instead of the SS pin.

Now, I realized that SS pin worked abnormally. See the above capture file.

SS pin should have gone down continually while Clk signal was working.

But, SS pin went up and down at all times.

So, I changed SS pin to GPIO and GPIO worked correctly.

Finally I could check ethernet switch driver family ID by MISO signal.

However, GPIO signal was also wired.

Going down timing was different at all times.

Anyway I want that this information help to every developer at least a little help...

Best regards,

Colin