Dear NXP experts,
according the Reference Manual of iMX8QXP (section 8.11.3.2, table 8-17), the MIPI DSI PLL has a fixed value of 864 MHz.
In the kernel dtsi, I can find the the declaration of mipi_pll_div2_clk as 432 MHz, half of the value declared in the Reference Manual.
Apparently, setting it to 864 MHz make no real changes: is this a fixed value because of a "div2" block ?
Given the mipi_pll_div2_clk at 432 MHz, which is the maximum display resolution for MIPI DSI ?
Thanks
Best Regards
Pier
Solved! Go to Solution.
Hi @pierluigi_p
mipi_pll_div2_clk: clk is half of source pll.
You can find the maximum display resolution for MIPI DSI in datasheet.
Programmable display resolutions, from 160x120(QQVGA) to
1920x1200(WUXGA) @ 60 fps, 24bpp
Hi @pierluigi_p
mipi_pll_div2_clk: clk is half of source pll.
You can find the maximum display resolution for MIPI DSI in datasheet.
Programmable display resolutions, from 160x120(QQVGA) to
1920x1200(WUXGA) @ 60 fps, 24bpp
Let us explore 1920x1080@60 Hz with RGB24.
display-timings {
native-mode = <&timing0>;
timing0: 1080p24 {
/* 1920x1080p24 */
clock-frequency = <52000000>;
hactive = <1920>;
vactive = <1080>;
hfront-porch = <25>;
hback-porch = <25>;
hsync-len = <25>;
vback-porch = <2>;
vfront-porch = <2>;
vsync-len = <2>;
hsync-active = <1>;
};
(1920+25+25+25)x(1080+2+2+2)x60Hz = 1995x1086x60 = pclk 1299994200 MHz per lane (roughly 130 MHz).
Since we have simultaneously 4 lanes, to transport RGB24 we need 6 clocks, which gives us 130 MHz x 6 = 780 Mbit/s.
Roughly, 1920x1200 is around 792 Mbit/s < 800 MHz, defined per NXP as maximum MIPI DSI DPHY freq... Instead of 144 MHz x 6 = 864 MHz, as theoretical possibility, which NXP was never able to achieve due to the technology limitations.
Well!
Zoran
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