imx8mm M4 vs Linux gpio interrupt flag clear

matt67 · ‎11-27-2019

Hello,

We are using the imx8mm evaluation board with Linux 4.14 and a DTS based on the evk-m4 (with more disabled things), which is the following:

  /*
   * Copyright 2018 NXP
   *
   * This program is free software; you can redistribute it and/or
   * modify it under the terms of the GNU General Public License
   * as published by the Free Software Foundation; either version 2
   * of the License, or (at your option) any later version.
   *
   * This program is distributed in the hope that it will be useful,
   * but WITHOUT ANY WARRANTY; without even the implied warranty of
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   * GNU General Public License for more details.
   */

  /dts-v1/;

  #include "fsl-imx8mm.dtsi"

  / {
   model = "FSL i.MX8MM EVK board";
   compatible = "fsl,imx8mm-evk", "fsl,imx8mm";

   chosen {
    bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
    stdout-path = &uart2;
   };
   

   reserved-memory {
    #address-cells = <2>;
    #size-cells = <2>;
    ranges;

    m4_reserved: m4@0x80000000 {
     no-map;
     reg = <0 0x80000000 0 0x1000000>;
    };

   };
   
   regulators {
    compatible = "simple-bus";
    #address-cells = <1>;
    #size-cells = <0>;

    reg_sd1_vmmc: sd1_regulator {
     compatible = "regulator-fixed";
     regulator-name = "WLAN_EN";
     regulator-min-microvolt = <3300000>;
     regulator-max-microvolt = <3300000>;
     gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
     off-on-delay = <20000>;
     startup-delay-us = <100>;
     enable-active-high;
    };

    reg_usdhc2_vmmc: regulator-usdhc2 {
     compatible = "regulator-fixed";
     regulator-name = "VSD_3V3";
     regulator-min-microvolt = <3300000>;
     regulator-max-microvolt = <3300000>;
     gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
     off-on-delay = <20000>;
     enable-active-high;
    };
   };
  };

  &clk {
   assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
   assigned-clock-rates = <786432000>, <722534400>;
  };

  &iomuxc {
   pinctrl-names = "default";

   imx8mm-evk {

    pinctrl_fec1: fec1grp {
     fsl,pins = <
      MX8MM_IOMUXC_ENET_MDC_ENET1_MDC  0x3
      MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
      MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
      MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
      MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
      MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
      MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
      MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
      MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
      MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
      MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
      MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
      MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
      MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
      MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
     >;
    };

    pinctrl_flexspi0: flexspi0grp {
     fsl,pins = <
      MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK  0x1c2
      MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B  0x82
      MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0  0x82
      MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1  0x82
      MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2  0x82
      MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3  0x82
     >;
    };

    pinctrl_i2c1: i2c1grp {
     fsl,pins = <
      MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL   0x400001c3
      MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA   0x400001c3
     >;
    };

    pinctrl_i2c2: i2c2grp {
     fsl,pins = <
      MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL   0x400001c3
      MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA   0x400001c3
     >;
    };

    pinctrl_pmic: pmicirq {
     fsl,pins = <
      MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3  0x41
     >;
    };

    pinctrl_typec1: typec1grp {
     fsl,pins = <
      MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
     >;
    };

    pinctrl_typec2: typec2grp {
     fsl,pins = <
      MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x159
     >;
    };

    pinctrl_uart2: uart2grp {
     fsl,pins = <
      MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
      MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
     >;
    };

    pinctrl_usdhc1_gpio: usdhc1grpgpio {
     fsl,pins = <
      MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
     >;
    };

    pinctrl_usdhc1: usdhc1grp {
     fsl,pins = <
      MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK  0x190
      MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD  0x1d0
      MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
      MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
      MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
      MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
     >;
    };

    pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
     fsl,pins = <
      MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK  0x194
      MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD  0x1d4
      MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
      MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
      MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
      MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
     >;
    };

    pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
     fsl,pins = <
      MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK  0x196
      MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD  0x1d6
      MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
      MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
      MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
      MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
     >;
    };

    pinctrl_usdhc2_gpio: usdhc2grpgpio {
     fsl,pins = <
      MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
      MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
     >;
    };

    pinctrl_usdhc2: usdhc2grp {
     fsl,pins = <
      MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK  0x190
      MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD  0x1d0
      MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
      MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
      MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
      MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
      MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
     >;
    };

    pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
     fsl,pins = <
      MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK  0x194
      MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD  0x1d4
      MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
      MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
      MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
      MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
      MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
     >;
    };

    pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
     fsl,pins = <
      MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK  0x196
      MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD  0x1d6
      MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
      MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
      MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
      MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
      MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
     >;
    };

    pinctrl_usdhc3: usdhc3grp {
     fsl,pins = <
      MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK  0x190
      MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD  0x1d0
      MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0  0x1d0
      MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1  0x1d0
      MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2  0x1d0
      MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3  0x1d0
      MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4  0x1d0
      MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5  0x1d0
      MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6  0x1d0
      MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7  0x1d0
      MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
     >;
    };

    pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
     fsl,pins = <
      MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK  0x194
      MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD  0x1d4
      MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0  0x1d4
      MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1  0x1d4
      MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2  0x1d4
      MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3  0x1d4
      MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4  0x1d4
      MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5  0x1d4
      MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6  0x1d4
      MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7  0x1d4
      MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
     >;
    };

    pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
     fsl,pins = <
      MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK  0x196
      MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD  0x1d6
      MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0  0x1d6
      MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1  0x1d6
      MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2  0x1d6
      MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3  0x1d6
      MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4  0x1d6
      MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5  0x1d6
      MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6  0x1d6
      MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7  0x1d6
      MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
     >;
    };

    pinctrl_wdog: wdoggrp {
     fsl,pins = <
      MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B  0xc6
     >;
    };
   };
  };


  &flexspi {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_flexspi0>;
   status = "okay";

   flash0: mt25qu256aba@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "micron,mt25qu256aba";
    spi-max-frequency = <29000000>;
    spi-nor,ddr-quad-read-dummy = <6>;
   };
  };

  &i2c1 {
   clock-frequency = <400000>;
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_i2c1>;
   status = "okay";

   pmic: bd71837@4b {
    reg = <0x4b>;
    compatible = "rohm,bd71840", "rohm,bd71837";
    /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
    pinctrl-0 = <&pinctrl_pmic>;
    gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;

    gpo {
     rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
    };

    regulators {
     #address-cells = <1>;
     #size-cells = <0>;

     bd71837,pmic-buck2-uses-i2c-dvs;
     bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */

     buck1_reg: regulator@0 {
      reg = <0>;
      regulator-compatible = "buck1";
      regulator-min-microvolt = <700000>;
      regulator-max-microvolt = <1300000>;
      regulator-boot-on;
      regulator-always-on;
      regulator-ramp-delay = <1250>;
     };

     buck2_reg: regulator@1 {
      reg = <1>;
      regulator-compatible = "buck2";
      regulator-min-microvolt = <700000>;
      regulator-max-microvolt = <1300000>;
      regulator-boot-on;
      regulator-always-on;
      regulator-ramp-delay = <1250>;
     };

     buck3_reg: regulator@2 {
      reg = <2>;
      regulator-compatible = "buck3";
      regulator-min-microvolt = <700000>;
      regulator-max-microvolt = <1300000>;
     };

     buck4_reg: regulator@3 {
      reg = <3>;
      regulator-compatible = "buck4";
      regulator-min-microvolt = <700000>;
      regulator-max-microvolt = <1300000>;
     };

     buck5_reg: regulator@4 {
      reg = <4>;
      regulator-compatible = "buck5";
      regulator-min-microvolt = <700000>;
      regulator-max-microvolt = <1350000>;
      regulator-boot-on;
      regulator-always-on;
     };

     buck6_reg: regulator@5 {
      reg = <5>;
      regulator-compatible = "buck6";
      regulator-min-microvolt = <3000000>;
      regulator-max-microvolt = <3300000>;
      regulator-boot-on;
      regulator-always-on;
     };

     buck7_reg: regulator@6 {
      reg = <6>;
      regulator-compatible = "buck7";
      regulator-min-microvolt = <1605000>;
      regulator-max-microvolt = <1995000>;
      regulator-boot-on;
      regulator-always-on;
     };

     buck8_reg: regulator@7 {
      reg = <7>;
      regulator-compatible = "buck8";
      regulator-min-microvolt = <800000>;
      regulator-max-microvolt = <1400000>;
      regulator-boot-on;
      regulator-always-on;
     };

     ldo1_reg: regulator@8 {
      reg = <8>;
      regulator-compatible = "ldo1";
      regulator-min-microvolt = <3000000>;
      regulator-max-microvolt = <3300000>;
      regulator-boot-on;
      regulator-always-on;
     };

     ldo2_reg: regulator@9 {
      reg = <9>;
      regulator-compatible = "ldo2";
      regulator-min-microvolt = <900000>;
      regulator-max-microvolt = <900000>;
      regulator-boot-on;
      regulator-always-on;
     };

     ldo3_reg: regulator@10 {
      reg = <10>;
      regulator-compatible = "ldo3";
      regulator-min-microvolt = <1800000>;
      regulator-max-microvolt = <3300000>;
      regulator-boot-on;
      regulator-always-on;
     };

     ldo4_reg: regulator@11 {
      reg = <11>;
      regulator-compatible = "ldo4";
      regulator-min-microvolt = <900000>;
      regulator-max-microvolt = <1800000>;
      regulator-boot-on;
      regulator-always-on;
     };

     ldo6_reg: regulator@13 {
      reg = <13>;
      regulator-compatible = "ldo6";
      regulator-min-microvolt = <900000>;
      regulator-max-microvolt = <1800000>;
      regulator-boot-on;
      regulator-always-on;
     };
    };
   };
  };

  &i2c2 {
   clock-frequency = <400000>;
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_i2c2>;
   status = "okay";

   adv_bridge: adv7535@3d {
    compatible = "adi,adv7533";
    reg = <0x3d>;
    adi,addr-cec = <0x3b>;
    adi,dsi-lanes = <4>;
    status = "okay";

    port {
     adv7535_from_dsim: endpoint {
      remote-endpoint = <&dsim_to_adv7535>;
     };
    };
   };

   typec1_ptn5110: tcpci@50 {
    compatible = "usb,tcpci";
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_typec1>;
    reg = <0x50>;
    interrupt-parent = <&gpio2>;
    interrupts = <11 8>;
    src-pdos = <0x380190c8>;
    snk-pdos = <0x380190c8>;
    /* Only can sink 5V for safe */
    max-snk-mv = <5000>;
    max-snk-ma = <3000>;
    op-snk-mw = <10000>;
    max-snk-mw = <15000>;
    port-type = "drp";
    default-role = "sink";
    status = "okay";
   };

   typec2_ptn5110: tcpci@52 {
    compatible = "usb,tcpci";
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_typec2>;
    reg = <0x52>;
    interrupt-parent = <&gpio2>;
    interrupts = <12 8>;
    src-pdos = <0x380190c8>;
    snk-pdos = <0x380190c8>;
    /* Only can sink 5V for safe */
    max-snk-mv = <5000>;
    max-snk-ma = <3000>;
    op-snk-mw = <10000>;
    max-snk-mw = <15000>;
    port-type = "drp";
    default-role = "sink";
    status = "okay";
   };
  };


  &mipi_csi_1 {
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };


  &lcdif {
   status = "disabled";
  };

  &mipi_dsi {
   status = "disabled";

   port@1 {
    dsim_to_adv7535: endpoint {
     remote-endpoint = <&adv7535_from_dsim>;
    };
   };
  };

  &mu {
   status = "okay";
  };

  &rpmsg{
   /*
    * 64K for one rpmsg instance:
    * --0xb8000000~0xb800ffff: pingpong
    */
   vdev-nums = <1>;
   reg = <0x0 0xb8000000 0x0 0x10000>;
   status = "okay";
  };

  &fec1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_fec1>;
   phy-mode = "rgmii-id";
   phy-handle = <&ethphy0>;
   fsl,magic-packet;
   status = "okay";

   mdio {
    #address-cells = <1>;
    #size-cells = <0>;

    ethphy0: ethernet-phy@0 {
     compatible = "ethernet-phy-ieee802.3-c22";
     reg = <0>;
     at803x,led-act-blind-workaround;
     at803x,eee-okay;
     at803x,vddio-1p8v;
    };
   };
  };

  &pcie0{
   status = "disabled";
  };


  &uart2 { /* console */
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_uart2>;
   status = "okay";
  };

  &uart3 {
   status = "disabled";
  };

  &usbotg1 {
   dr_mode = "otg";
   extcon = <0>, <&typec1_ptn5110>;
   picophy,pre-emp-curr-control = <3>;
   picophy,dc-vol-level-adjust = <7>;
   status = "okay";
  };

  &usbotg2 {
   dr_mode = "otg";
   extcon = <0>, <&typec2_ptn5110>;
   picophy,pre-emp-curr-control = <3>;
   picophy,dc-vol-level-adjust = <7>;
   status = "disabled";
  };

  &usdhc1 {
   pinctrl-names = "default", "state_100mhz", "state_200mhz";
   pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
   pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
   pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
   bus-width = <4>;
   vmmc-supply = <&reg_sd1_vmmc>;
   pm-ignore-notify;
   keep-power-in-suspend;
   non-removable;
   status = "okay";
  };

  &usdhc2 {
   pinctrl-names = "default", "state_100mhz", "state_200mhz";
   pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
   pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
   pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
   cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
   bus-width = <4>;
   vmmc-supply = <&reg_usdhc2_vmmc>;
   status = "okay";
  };

  &usdhc3 {
   pinctrl-names = "default", "state_100mhz", "state_200mhz";
   pinctrl-0 = <&pinctrl_usdhc3>;
   pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
   pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
   bus-width = <8>;
   non-removable;
   status = "okay";
  };

  &wdog1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_wdog>;
   fsl,ext-reset-output;
   status = "okay";
  };

  &A53_0 {
   arm-supply = <&buck2_reg>;
  };

  &gpu {
   status = "okay";
  };

  &vpu_g1 {
   status = "okay";
  };

  &vpu_g2 {
   status = "okay";
  };

  &vpu_h1 {
   status = "okay";
  };

  &sdma1{
  status = "disabled";
  };

  &uart4 {
  status = "disabled";
  };

  &sdma3 {
  status = "disabled";
  };

  &sai1 {
  status = "disabled";
  };

  &flexspi {
  status = "disabled";
  };



‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

On the M4 side, we run a firmware that handles some GPIOs routed from the expansion header.

One is the GPIO3 IO22, from the pad SAI5_RXD1, configured in input with interruption.

The problem, is that in the handler the flag (GPIO3_ISR) is automatically cleared if Linux is running, and leads to a Linux hang if we clear it in the same time.

/* GPIO3 IRQ Handler */
void GPIO3_Combined_16_31_IRQHandler(void)
{

    if ((BOARD_GPIO_3->IMR | BOARD_GPIO_3_S2LP_IRQ_CONFIG_MASK) != 0)
    {
        // Tmp remove code for debugging...
    }

    // Clear flag
    GPIO_ClearPinsInterruptFlags(BOARD_GPIO_3, BOARD_GPIO_3_S2LP_IRQ_CONFIG_MASK);
}
‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

On the device tree, there is absolutely no mention to any GPIO3, so I can't understand why is Linux clearing the flag.

Any idea ?

matt67 · ‎12-03-2019

Hello,

Thanks for reply.

Solution was found, in fact the GPIO3 is declared in fsl-imx8mm.dtsi :

 gpio3: gpio@30220000 {
  compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  reg = <0x0 0x30220000 0x0 0x10000>;
  interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-controller;
  #interrupt-cells = <2>;
 };‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

This result in loading the gpio3 device in the driver gpio-mxs.c and the IRQ handler is clearing the flag when interrupt occurs on any GPIO of this bank :

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(struct irq_desc *desc)
{
 u32 irq_stat;
 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);

 desc->irq_data.chip->irq_ack(&desc->irq_data);

 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
   readl(port->base + PINCTRL_IRQEN(port));

 while (irq_stat != 0) {
  int irqoffset = fls(irq_stat) - 1;
  if (port->both_edges & (1 << irqoffset))
   mxs_flip_edge(port, irqoffset);

  generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
  irq_stat &= ~(1 << irqoffset);
 }
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

If this occurs in the same time on the Cortex-M4 firmware side, Linux hangs.

The solution is then to disable the whole GPIO3 in our board device tree :

 &gpio3 {
 status = "disabled";
 };‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

To prevent such things, we are protecting all the imx8 M4 peripherals with the Rdc domain assignments.

Example of the Rdc can be found on MCUExpresso "rdc.zip".

View solution in original post

matt67 · ‎12-03-2019

Hello,

Thanks for reply.

Solution was found, in fact the GPIO3 is declared in fsl-imx8mm.dtsi :

 gpio3: gpio@30220000 {
  compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  reg = <0x0 0x30220000 0x0 0x10000>;
  interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-controller;
  #interrupt-cells = <2>;
 };‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

This result in loading the gpio3 device in the driver gpio-mxs.c and the IRQ handler is clearing the flag when interrupt occurs on any GPIO of this bank :

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(struct irq_desc *desc)
{
 u32 irq_stat;
 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);

 desc->irq_data.chip->irq_ack(&desc->irq_data);

 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
   readl(port->base + PINCTRL_IRQEN(port));

 while (irq_stat != 0) {
  int irqoffset = fls(irq_stat) - 1;
  if (port->both_edges & (1 << irqoffset))
   mxs_flip_edge(port, irqoffset);

  generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
  irq_stat &= ~(1 << irqoffset);
 }
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

If this occurs in the same time on the Cortex-M4 firmware side, Linux hangs.

The solution is then to disable the whole GPIO3 in our board device tree :

 &gpio3 {
 status = "disabled";
 };‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

To prevent such things, we are protecting all the imx8 M4 peripherals with the Rdc domain assignments.

Example of the Rdc can be found on MCUExpresso "rdc.zip".

igorpadykov · ‎11-28-2019

Hi matt67

gpio3_16 is used as led in

fsl-imx8mm-evk.dts\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel

pad SAI5_RXD1 can be used as PDM_DATA1.

Also may be useful to rebuild all image from scratch.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

imx8mm M4 vs Linux gpio interrupt flag clear

imx8mm M4 vs Linux gpio interrupt flag clear

i.MX 8M | i.MX 8M Mini | i.MX 8M Nano