Hello, All
TOOLS:
MX8QXP_C0_B0_LPDDR4_RPA_1.2GHz_v13.xlsx
mx8_ddr_stress_test_ER14_installation.zip
BOARD: Imx8qxp mek DDR stress test
LPDDR4 3G --->4G
test log:
*************************************************************************
MX8 DDR Stress Test Version: ER14
Built on Mar 27 2020 12:28:23
*************************************************************************
-Set up the MMU and enable I and D cache-
*************************************************************************
ARM Clock(CA35): 1200MHz
DDR Clock: 1200MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 4096MB
Total density detected on the board is: 4096MB
No DDR data training errors detected for DDRC0
============================================
MX8QXP: Cortex-A35 is found
*************************************************************************
DDR Stress Test Iteration 1
--------------------------------
-Running DDR test on region 1-
--------------------------------
t0.1: data is addr test
....
t0.2: row hop read test
...
t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...
t5: IRAM_to_DDRv2 test
--------------------------------
-Running DDR test on region2-
--------------------------------
t0.1: data is addr
(Stuck here, didn't know it was wrong, stayed there for 20 minutes, restarted the test many times and still did the same thing)
Hi Wang
one can recheck "BoardDataBusConfig" settings in RPA tool and
tweak drive strength settings.
Best regards
igor
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hello, igor
I don't know why I pressed the download button of the case. Now it is shown in the picture, and there is no other display
tks
hello, igor
can you tell me how to setting "BoardDataBusConfig"?
only modify
Density per channel per chip select (Gb)1: | 6 |
to 8.
tks