imx6 quad vs dual => uboot

[jaiganesh]

Hi all,

          We are building a custom board using imx6 dual processor (with the same 1GB RAM chip as in sabresd) and we have mx6qsabresd as the reference board. I just wanted to know, is there any change to be done in u-boot in sabresd BSP (especially in the DCD items) for our custom board or the u-boot.imx built for mx6qsabresd is sufficient enough for a dual processor?

       I know u-boot should be modified according to the peripherals we are using in our board. But I am just asking, about basic initialization difference between quad core and dual core of imx6 processors at the u-boot level.

Thanks,

Jai Ganesh S

[repoman]

Jai,

I have a custom board with an I.MX6Q and I believe the Dual and Quad Core (as long as it is not a dual lite) have the same MMDC controller.  This means that the DCD information should be very similar.

I started with references such as the sabresd BSP as well and worked my way from there.  In this forum, there are some posts and a DDR Stress Tester.  I think version 1.0.3 is the latest.  I used that to fine tune the calibration (not that my board was much different).  However, I did layout all four ram chips on the top layer of the board for long term cooling perspective and I used a T bus topology.  So the initialization could have been a lot different depending on which route you chose for the DDR memory.  If you kept it similar to the Freescale recommended layout of two chips on top and two chips on bottom, then I bet it will be extremely similar.

However, the Dual and Quad

R,
John

[jaiganesh]

John,

          Thanks for you answer. You said, based on how we layout the DDR chips in the board, RAM initialization will vary. I have gone through all the registers specified in the file "mx6q_4x_mt41j128.cfg" (which is basically the DDR configuration registers) for sabresd, but it seems there is no register that tells any information on DDR layout.Meanwhile I am not much sure of purpose of each register in detail (As far as I know, they were all related to some kind of DDR timing information). So I will go through those once again.

And it seems your last sentence is breaked. You were saying something like "However, the Dual and Quad" in the last, but I guess it is not completed (or breaked). Is there anything you meant to say at that last sentence?

[repoman]

Jai,

What I was getting at about DDR is that the DCD registers and the calibration settings are actually taking into account the physical layout of the I.MX SoC to the DDR memory devices.  There is no specific register or anything that can tell you about which layout.  All of the registers collectively adjust the relative time delays of the signal groups within the DDR2/DDR3 protocol interface.  Other parameters are also set such as the termination value for the on die termination (ODT) items that pertain to DDR2/DDR3 memory types.  If you are using similar DDR3 to the SabreSD than most of these values will be exactly the same and no change is required.

I definitely left a broken sentence.  I was just going to reiterate that the Dual and Quad chip sets are the same with respect to the MMDC controller.  This means that the DCD configuration for the sabre boards found with the mx6q_4x_mt41j128.cfg should be close enough to get the board initially operating.  I would definitely advise using the DDR Stress Test tool to calibrate the values once it is up and running (https://community.freescale.com/docs/DOC-96412).  Calibration can ensure that the initialization information for the controller is optimized for both temperature variations and operating frequency variations. For further information, please refer to the I.MX Dual/Quad Reference manual (IMX6DQRM) published by Freescale; Chapter 44 pertains to the Multi Mode DDR Controller (MMDC).

I have very recently had to do both of these things.  I started with the Freescale SDK and ported my board into that system for very initial bringup.  I used the DCD file from the SabreSD similar to what you are talking about.  The SDK allows for hardware checks but you have to dig into the code base to really add in a board.  After I was done running many of the SDK built in tools, I then moved to using U boot.  I compiled the latest U-Boot (for no other reason than I eventually want to push my board back up to U boot).  I started with the reference .cfg file similar to what you called out. These all worked fine and I didn't experience any grave difficulties with these starting files.  However, I did want to do my due diligence and so I ran the DDR Stress test tool so that I could get the appropriate calibration parameters and inserted those into the .cfg for u boot and the DCD.c in the SDK.  I have not experienced many changes as the calibrated "new" values are not extremely different from the original but with the original values the stress tester would only run at 528Mhz which means that I was on the margin and just happened to be "lucky" that the original values in the .cfg file worked on this board.

Hope this helps and sorry for the broken statement,

John

[jaiganesh]

Thanks John and sorry for the late reply. Seems there wont be much in our .cfg file since we will be using same kind of RAM as in sabresd. We will get our custom board within three weeks and hope initial bringup will go smooth since RAM is similar.

Thanks again,

Jai Ganesh