imx6 dual: how to map hsync/vsync/data enable to different pins

[angelos]

Hi all,

I'm currently working on a custom board based on imx6 Dual.

Linux version 3.10.17_1.0.0_ga.

Display info:

+      "Disp1", 60, 800, 480, 30300,

+      216, 40,

+      32, 13,

+      20, 10,

+      0,

+      FB_VMODE_NONINTERLACED,

+      0},

I have the following needs:

HSYNC -> DI0_PIN08

VSYNC -> DI0_PIN11

DE -> DI0_PIN12

How can I do that?

At the moment I've configured HSYNC with the following changes:

* ipu_disp.c

* _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC_PIN8, h_total - 1,

                                  DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK, 

                                  0, DI_SYNC_NONE, 1, DI_SYNC_NONE, 

                                  DI_SYNC_CLK, 0, h_sync_width * 2);

but VSYNC and DE are not generated.

Thanks in advance!

In addition ti this, I would like to understand the Table 52. Video Signal Cross-Reference in the data sheet (MX6DQCPOPEC) :

PINS 11 and 12 are reported in the following way:

IPUx_DIx_PIN11 — —

IPUx_DIx_PIN12 — —

What's the meaning of  "—"?

[alejandrolozan1]

Hi,

The below discussion may be helpful.

How to change IMX53 VGA HSYNC from DI1_PIN7 to DI1_PIN4 -blog archive

I know it is with a different kernel version I believe you may find it helpful.

Futhermore you have to keep in mind that you have to modify the dts  or dtsi files to use those pins.

For example, by default, the sabresd uses the next pins for the LCD interface.

pinctrl_ipu1_1: ipu1grp-1 {

                        fsl,pins = <

                                MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10

                                MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10

                                MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10

                                MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10

                                MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000

                                MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10

                                MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10

                                MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10

                                MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10

                                MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10

                                MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10

                                MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10

                                MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10

                                MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10

                                MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10

                                MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10

                                MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10

                                MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10

                                MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10

                                MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10

                                MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10

                                MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10

                                MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10

                                MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10

                                MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10

                                MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10

                                MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10

                                MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10

                                MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10

                        >;

                };

Please make sure that you use your corresponding DI_PIN for the needed purposes.

Best Regards,

Alejandro

[angelos]

Hi,

thanks for your feedback!

I saw this discussion but I need some feedback from Freescale regarding

In addition ti this, I would like to understand the Table 52. Video Signal Cross-Reference in the data sheet (MX6DQCPOPEC) :

PINS 11 and 12 are reported in the following way:

IPUx_DIx_PIN11 — —

IPUx_DIx_PIN12 — —

What's the meaning of  "—"?

This is an official document released from Freescale so, I'd like to get an official feedback :smileygrin:

[alejandrolozan1]

Hi,

As you can see the table just provides examples. If you find content in those fields it is just an example for the control lines, if there is no content it means nothing (they are not used in that example).

But the pins are flexible.

/Alejandro