iMx8M Nano - Data Bus Invertion (DBI) on DDR4 is avaliable ?

[sergiospader]

Good Morning,

I found some notes saying that for better HW performance I should be using DBI feature at DDR4.

I could not find out if it is available @ iMx8M and found no information on how to configure it, can you help ?

We are having some DDR4 errors in high temperature and we wan't to test if it increase the DDR performance in our system

Thanks

Sérgio 

[nxf63675]

Hi @sergiospader,

Yes, it is possible to use DBI on i.MX8M nano, the last release of the tool fix some bugs that can not allow the correct function on this.

You need to modify the next cells in order to get this working.

RD_DBI_EN	-	0	00000000	Read DBI enable signal in DDRC. ■0 - Read DBI is disabled. ■1 - Read DBI is enabled. This signal must be set the same value as DRAM's mode register. ■DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. ■LPDDR4: MR3[6] Value After Reset: 0x0
WR_DBI_EN	-	0	00000000	Write DBI enable signal in DDRC. ■0 - Write DBI is disabled. ■1 - Write DBI is enabled. This signal must be set the same value as DRAM's mode register. ■DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. ■LPDDR4: MR3[7] Value After Reset: 0x0

Regards,

Israel.

[estiven]

Hi Israel @nxf63675,

I work together with @sergiospader.

I changed the cells you suggested to use the DBI in the MX8M_Nano_DDR4_RPA_v6.xlsx worksheet, but with this change an error appears after calibrating the DDR in the Mscale DDR Tool software.

Follow Mscale error:

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1200Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1200Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1200MHz......Address of failure: 0x0000000040080000
Data read was: 0xFFFFFFFFBFFFFFFF
But pattern was: 0x0000000040000000
Failed
Please modify DDRC/DFI parameters!!!

Without this change to use DBI I can calibrate and run the Stress Test.

Would it be necessary to change some other cell in the worksheet or perform some other configuration to use DBI?

Regards,

Estiven

[nxf63675]

Hi @estiven,

Usually this kind of errors can be fixed by modifing ODTImpedance to a larger one. Re-run the calibration and see if this work for you.

Regards,

Israel.

[estiven]

Hi Israel @nxf63675,

Just increasing ODTImpedance didn't work. Would I need to change any more cells to work?

Should I enable PHY_DBI_MODE too?

PHY_DBI_MODE

-

0

00000000

Description: DBI implemented in DDRC or PHY. ■0 - DDRC implements DBI functionality. ■1 - PHY implements DBI functionality. Present only in designs configured to support DDR4 and LPDDR4. Value After Reset: 0x0

Best Regards,

Estiven

[nxf63675]

Hi @estiven,

Which version of the DDR tool are you using?

Regards,

Israel.

[estiven]

Hi Israel @nxf63675,

I'm using the version 3.3 (mscale_ddr_tool _v3.30_setup.exe.zip)

Regards,

Estiven

[nxf63675]

Thanks for the confirmation @estiven, I will check with the developers of the tool why this is not working for you, just one more thing, the board you are using, is our EVK or is the your own design?

Regards,

Israel.

[estiven]

Hi Israel @nxf63675,

We are using the our own design.

Thank you for your attention to our question

Regards,

Estiven

[nxf63675]

Hi @estiven and @sergiospader,

After reviewing the info from the designers the tool supports the DBI and works on our EVK's, I tested by myself and works, as this is a custom design you should review and check the Hardware developers guide and compare to our design of the i.MX8M Nano to see what is the main differences.https://www.nxp.com/webapp/Download?colCode=8MNANOD4-EVK-DF-SCH

Regards,

Israel.

[estiven]

Hi Israel @nxf63675,

We purchased the 8MNANOD4-EVK kit and when trying to enable DBI we get the same result using Mscale 3.3:
---------------------------------------------------------------------------------------------
============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1200MHz......Address of failure: 0x0000000040080000
Data read was: 0xFFFFFFFFBFFFFFFF
But pattern was: 0x0000000040000000
failed
Please modify DDRC/DFI parameters!!!
---------------------------------------------------------------------------------------------

Could you send me the spreadsheet you used in your EVM tests? or could you indicate exactly which fields were changed in the worksheet for the DBI to work?
Was it necessary to change the READ Latency (CL) because of DBI?

We are using version 8 spreadsheet with default configuration MX8M_Nano_DDR4_RPA_v8.xlsx

Best Regards,

Estiven

[estiven]

Hi Israel @nxf63675,

Thanks for the answer. I compared our design with the EVK and it doesn't have many significant changes.
In the MX8M_Nano_DDR4_RPA_v7.xlsx worksheet, did you just change the fields "RD_DBI_EN" and "WR_DBI_EN" to enable DBI and nothing else? Was it necessary to change the "CL" or something?

Regards,

Estiven