Hello,
I'm trying to enable the CA parity function with "MX8M_Mini_DDR4_RPA_v15.xlsx". I changed the parity_enable bit from '0' to '1' in the D155 cell. From the DDR tool testing, I met below calibration error. What else settings in the RPA file should be changed? Please advise. Thanks.
Best Regards,
Jeff
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ARM clock(CA53) rate: 1800MHz
DDR Clock: 1200MHz
============================================
DDR configuration
DDR type is DDR4
Data width: 32, bank num: 8
For DDR4, bank num is the total of 2 bank groups and 4 banks per group
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================
MX8M-mini: Cortex-A53 is found
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============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1200Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @668Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1200Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS
============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1200MHz......Address of failure: 0x0000000040080000
Data read was: 0x00F10000FFFF42F0
But pattern was: 0x0000000040000000
Failed
Please modify DDRC/DFI parameters!!!
