iMX6QP SPDIF TX using ASRC_EXT_CLK

[camilio69]

In the Reference Manual §60.5.18, TxClk_Source of SPDIF_STC can be set to 2 (010) to select ASRC_EXT_CLK input.

However, in the GPR0 register (RM §36.4.1) bits 14-15 (TX_CLK2_MUX_SEL) pretends to select this clock as the ASRC internal clocks 1,2 or 3, so not the external PAD.

From my tests on a custom board, it really looks like this clock is not connected to the ASRC_EXT_CLK pad (and I am sure of pin muxing, as it works for use in ASRC).

Does anyone know which part tells the truth ?

Thanks,

[camilio69 · Accepted solution]

Finally, I solved this myself after making some board changes, and I confirm that the GPR0 settings decides the clock source for SPDIF TX clock 2.

So it is not possible to use the ASRC_EXT_PAD as clock source for the SPDIF TX, but it is possible to use any of the AUDMUX TXC or RXC by routing them properly in AUDMUX and selecting which to use from GPR0.

For instance, if you want to use AUD4_TXC to clock the SPDIF TX, you can route it to AUDMUX port 1 RXC output, and use it as ASRC clock 1 (GPR0.CLOCK_1_MUX_SEL=01) and tell the SPDIF TX to use this as clock 2 (GPR0.TX_CLK2_MUX_SEL=00).

Of course, one can also use directly SPDIF_EXT_PAD for a secondary frequency (if you want a clock for 44.1kHz and 48kHz, or different clock domains), which is straight forward.