iMX6L lack of DDR clock

[takafuminaka]

Hello,

We observed the lack of DDR base clock.

The clock periodically stops( 0V ).

It seems the cycle is in synchronization with LCD display's VSYNC and HSYNC.

We attached the waveform.

Could you let us know the reason about this issue?

Is this normal behavior?

Thank you.

[igorpadykov]

Hi Takafumi

if customer does not have other issues (such as OS hanging

ot other misbehaviour), then this seems as normal

behaviour. Becasue during VSYNC,HSYNC i.MX6 does not fetch data

from memory, so there may be no DDR clock during LCD synch pulses.

Best regards

chip

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[takafuminaka]

Dear chipexpert ,

Thank you very much for your quick reply.

For supporting this issue, we set CCM_CLPCR[LPM] as 00.

But it doesn't have any impact on this issue.

Is there any other registers for using "Remain in run mode" setting?

[igorpadykov · Accepted solution]

This has not relation to low power modes.

During VSYNC,HSYNC i.MX6 does not fetch data

from memory, so there may be no DDR clock during LCD synch pulses.

Best regards

chip