Hi,
I'm looking to implement a high resolution timestamping function in the M4 cores of an i.MX8QM. Are you able to confirm whether the DWT cycle count (DWT_CYCCNT) is implemented on the i.MX8QM Cortex M4? Table 2-27 'PPB memory map' of the i.MX 8QuadMax Applications Processor Reference Manual, Rev. 0, 9/2021 shows the DWT memory allocation (E000_1000 to E000-1FFF) but doesn't provide any further detail. Do I just assume that the DWT implementation is per the Cortex M4 specification by ARM?
Thanks!
