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- Re: i.MX8MP: No video signal over HDMI but monitor detected
i.MX8MP: No video signal over HDMI but monitor detected
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Hello,
I'm trying to get HDMI working on a custom board, based on the i.MX8MP. The monitor is already recognized but it always shows "no signal". Does anyone have any idea how I can fix this and how I can get an image on the screen?
I can get information from the monitor:
cat /sys/devices/platform/display-subsystem/drm/card1/card1-HDMI-A-1/enabled
enabled
cat /sys/devices/platform/display-subsystem/drm/card1/card1-HDMI-A-1/status
connected
cat /sys/devices/platform/display-subsystem/drm/card1/card1-
HDMI-A-1/modes
1920x1200
1920x1080
1920x1080
1920x1080
1920x1080
1600x1200
...
In /sys/kernel/debug/clk/clk_summary it seems that the hdmi_phy does not have a clock?
cat /sys/kernel/debug/clk/clk_summary | grep "hdmi"
hdmi_ref_266m 1 1 0 24000000 0 0 50000
hdmi_glb_ref_266m 0 0 0 24000000 0 0 50000
hdmi_sec_mem 0 0 0 24000000 0 0 50000
hdmi_esm 0 0 0 24000000 0 0 50000
hdmi_24m 2 2 0 24000000 0 0 50000
hdmi_glb_24m 2 2 0 24000000 0 0 50000
hdmi_phy 2 2 0 0 0 0 50000
hdmi_glb_pix 5 5 0 0 0 0 50000
hdmi_pipe_sel 1 1 0 0 0 0 50000
hdmi_vid_pix 1 1 0 0 0 0 50000
hdmi_tx_pix 1 1 0 0 0 0 50000
hdmi_phy_sel 0 0 0 24000000 0 0 50000
hdmi_fdcc_tst 1 1 0 24000000 0 0 50000
hdmi_fdcc_ref 1 1 0 24000000 0 0 50000
hdmi_axi 3 3 0 500000000 0 0 50000
hdmi_glb_b 2 2 0 500000000 0 0 50000
hdmi_root_clk 1 1 0 500000000 0 0 50000
hdmi_apb 4 4 0 133333333 0 0 50000
hdmi_glb_apb 14 14 0 133333333 0 0 50000
hdmi_trng_apb 0 0 0 133333333 0 0 50000
hdmi_trng_skp 0 0 0 133333333 0 0 50000
hdmi_phy_int 1 1 0 133333333 0 0 50000
hdmi_phy_apb 1 1 0 133333333 0 0 50000
hdmi_tx_prep 1 1 0 133333333 0 0 50000
hdmi_tx_skp 1 1 0 133333333 0 0 50000
hdmi_tx_sfr 1 1 0 133333333 0 0 50000
hdmi_tx_gpa 1 1 0 133333333 0 0 50000
hdmi_tx_apb 1 1 0 133333333 0 0 50000
hdmi_tx_hpi 1 1 0 133333333 0 0 50000
hdmi_noc 1 1 0 133333333 0 0 50000
hdmi_irq_steer 1 1 0 133333333 0 0 50000
hdmi_glb_32k 1 1 0 32768 0 0 50000
hdmi_cec 1 1 0 32768 0 0 50000
In my dts file I have HDMI activated:
[ 1.836434] [drm] Initialized vivante 1.0.0 20170808 for 40000000.mix_gpu_ml on minor 0
[ 2.677455] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
[ 2.706143] imx-drm display-subsystem: bound 32fd8000.hdmi (ops dw_hdmi_imx_ops)
[ 2.718570] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1
[ 3.082745] imx-drm display-subsystem: [drm] fb0: imx-drmdrmfb frame buffer device
[ 0.158403] samsung-hdmi-phy 32fdff00.hdmiphy: failed to get phy apb clk: -517
[ 1.248637] imx-hdmi-pavi 32fc4000.hdmi-pai-pvi: No pvi clock get
[ 1.901349] imx-cdnhdmi sound-hdmi: snd_soc_register_card failed (-517)
[ 2.308144] samsung-hdmi-phy 32fdff00.hdmiphy: failed to get phy apb clk: -517
[ 2.666573] imx-cdnhdmi sound-hdmi: snd_soc_register_card failed (-517)
[ 2.685693] dwhdmi-imx 32fd8000.hdmi: Detected HDMI TX controller v2.13a with HDCP (samsung_dw_hdmi_phy2)
[ 2.696281] dwhdmi-imx 32fd8000.hdmi: registered DesignWare HDMI I2C bus driver
[ 2.706143] imx-drm display-subsystem: bound 32fd8000.hdmi (ops dw_hdmi_imx_ops)
Solved! Go to Solution.
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I finally have a solution. The problem was in hardware. We used an older HDMI Port Protection and Interface chip which only supported HDMI 1.3 after removing this chip and connecting the wires directly, the HDMI output worked.
joanxie
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what display do you use? it seems that current bsp doesn't support your HDMI resolution as default
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Thank you for your answer. I tried using my desktop monitor (1920x1200), a TV (1920x1080) via HDMI as well es 2 other screens via HDMI-DVI-adapters. None of which worked.
Output when my TV is connected:
cat /sys/devices/platform/display-subsystem/drm/card1/card1-HDMI-A-1/dpms
On
/tmp/root # cat /sys/devices/platform/display-subsystem/drm/card1/card1-HDMI-A-1/enabled
enabled
/tmp/root # cat /sys/devices/platform/display-subsystem/drm/card1/card1-HDMI-A-1/status
connected
/tmp/root # cat /sys/devices/platform/display-subsystem/drm/card1/card1-HDMI-A-1/edid
������M�\��Zx
ɠWG�'HL��:�q8-@X,E@�crQ� n(U@�c�SONY TV XV
�0>F
�+pP # �f
���9:��r8-@,E�@�c�R� �(U@@�c�q X,%@�c���r ,%�@�c��/tmp/root #
/tmp/root # cat /sys/devices/platform/display-subsystem/drm/card1/card1-HDMI-A-1/modes
1920x1080
1920x1080
1920x1080
1920x1080
1920x1080
1920x1080
1920x1080
1280x1024
1280x720
1280x720
1280x720
1280x720
1280x720
800x600
720x576
720x576
720x480
720x480
720x480
720x480
640x480
640x480
640x480
/tmp/root # dmesg | grep "hdmi"
[ 0.157965] samsung-hdmi-phy 32fdff00.hdmiphy: failed to get phy apb clk: -517
[ 1.245659] imx-hdmi-pavi 32fc4000.hdmi-pai-pvi: No pvi clock get
[ 1.894672] imx-cdnhdmi sound-hdmi: snd_soc_register_card failed (-517)
[ 2.297808] samsung-hdmi-phy 32fdff00.hdmiphy: failed to get phy apb clk: -517
[ 2.661089] imx-cdnhdmi sound-hdmi: snd_soc_register_card failed (-517)
[ 2.680176] dwhdmi-imx 32fd8000.hdmi: Detected HDMI TX controller v2.13a with HDCP (samsung_dw_hdmi_phy2)
[ 2.690962] dwhdmi-imx 32fd8000.hdmi: registered DesignWare HDMI I2C bus driver
[ 2.700081] imx-drm display-subsystem: bound 32fd8000.hdmi (ops dw_hdmi_imx_ops)
[ 3.095109] input: audio-hdmi HDMI Jack as /devices/platform/sound-hdmi/sound/card1/input4
[ 7.448005] #1: audio-hdmi
/tmp/root # dmesg | grep "drm"
[ 1.832519] [drm] Initialized vivante 1.0.0 20170808 for 40000000.mix_gpu_ml on minor 0
[ 2.671953] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
[ 2.700081] imx-drm display-subsystem: bound 32fd8000.hdmi (ops dw_hdmi_imx_ops)
[ 2.713153] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1
[ 3.078812] imx-drm display-subsystem: [drm] fb0: imx-drmdrmfb frame buffer device
joanxie
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could you tell me which display cause this error message? current bsp can support 1920x1080 as default, but doesn't support 1920x1200, but you need check if current hdmi driver supports your display clock or not, you can check this:
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All Displays I try cause the same message. This particular one was created when my board was connected to my1920x1080 TV.
I added some debug prints in phy-fsl-samsung-hdmi.c and now I can see that the driver loads successfully, and sets a clock rate of 154000000 (successfully - samsung_hdmi_phy_clk_set_rate sets 154000000 and exits with return code 0)
joanxie
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for 1920x1080 TV, could you dump the clock and share with me?
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The Clock Rate reported by the kernel is: 148500000
dmesg | grep "hdmi"
[ 0.166220] samsung-hdmi-phy 32fdff00.hdmiphy: failed to get phy apb clk: -517
[ 1.256890] imx-hdmi-pavi 32fc4000.hdmi-pai-pvi: No pvi clock get
[ 1.948497] imx-cdnhdmi sound-hdmi: snd_soc_register_card failed (-517)
[ 2.455014] samsung-hdmi-phy 32fdff00.hdmiphy: failed to get phy apb clk: -517
[ 2.914482] imx-cdnhdmi sound-hdmi: snd_soc_register_card failed (-517)
[ 2.921636] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] got phy apb clk
[ 2.927915] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] got phy refclk
[ 2.934103] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] enabled apbclk
[ 2.940367] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] HDMI PHY created
[ 2.946950] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] clk registered
[ 2.953137] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] phy registered successfully
[ 2.988489] dwhdmi-imx 32fd8000.hdmi: Detected HDMI TX controller v2.13a with HDCP (samsung_dw_hdmi_phy2)
[ 2.999222] dwhdmi-imx 32fd8000.hdmi: registered DesignWare HDMI I2C bus driver
[ 3.009568] imx-drm display-subsystem: bound 32fd8000.hdmi (ops dw_hdmi_imx_ops)
[ 3.233695] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] samsung_hdmi_phy_clk_set_rate: 148500000
[ 3.258741] samsung-hdmi-phy 32fdff00.hdmiphy: [SM] samsung_hdmi_phy_clk_set_rate: successful
This is how I added the additional prints for debugging:
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
index 5947cba737f8..eb0fb27bd027 100644
--- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
@@ -931,6 +931,8 @@ static int samsung_hdmi_phy_clk_set_rate(struct clk_hw *hw,
const struct phy_config *phy_cfg = samsung_phy_pll_cfg;
int i;
+ dev_err(samsung->dev, "[SM] samsung_hdmi_phy_clk_set_rate: %lu\n", rate);
+
dev_dbg(samsung->dev, "%s\n", __func__);
for (; phy_cfg->clk_rate != 0; phy_cfg++)
@@ -951,6 +953,8 @@ static int samsung_hdmi_phy_clk_set_rate(struct clk_hw *hw,
/* Wait for PHY PLL lock */
msleep(20);
+ dev_err(samsung->dev, "[SM] samsung_hdmi_phy_clk_set_rate: successful\n");
+
return 0;
}
@@ -1037,6 +1041,8 @@ static int samsung_hdmi_phy_probe(struct platform_device *pdev)
return ret;
}
+ dev_err(samsung->dev, "[SM] got phy apb clk\n");
+
samsung->refclk = devm_clk_get(samsung->dev, "ref");
if (IS_ERR(samsung->refclk)) {
ret = PTR_ERR(samsung->refclk);
@@ -1044,12 +1050,16 @@ static int samsung_hdmi_phy_probe(struct platform_device *pdev)
return ret;
}
+ dev_err(samsung->dev, "[SM] got phy refclk\n");
+
ret = clk_prepare_enable(samsung->apbclk);
if (ret) {
dev_err(samsung->dev, "failed to enable apbclk\n");
return ret;
}
+ dev_err(samsung->dev, "[SM] enabled apbclk\n");
+
samsung->phy = devm_phy_create(samsung->dev, NULL, &samsung_hdmi_phy_ops);
if (IS_ERR(samsung->phy)) {
ret = PTR_ERR(samsung->phy);
@@ -1057,6 +1067,8 @@ static int samsung_hdmi_phy_probe(struct platform_device *pdev)
goto phy_failed;
}
+ dev_err(samsung->dev, "[SM] HDMI PHY created\n");
+
phy_set_drvdata(samsung->phy, samsung);
phy_set_bus_width(samsung->phy, 8);
@@ -1066,6 +1078,8 @@ static int samsung_hdmi_phy_probe(struct platform_device *pdev)
goto phy_failed;
}
+ dev_err(samsung->dev, "[SM] clk registered\n");
+
phy_provider = devm_of_phy_provider_register(samsung->dev,
of_phy_simple_xlate);
if (IS_ERR(phy_provider)) {
@@ -1074,9 +1088,12 @@ static int samsung_hdmi_phy_probe(struct platform_device *pdev)
goto phy_failed;
}
+ dev_err(samsung->dev, "[SM] phy registered successfully\n");
+
return 0;
phy_failed:
+ dev_err(samsung->dev, "[SM] phy_failed\n");
clk_disable_unprepare(samsung->apbclk);
return ret;
}
Details from the TV (read out from edid and decoded):
edid-decode (hex):
00 ff ff ff ff ff ff 00 4d d9 01 5c 01 01 01 01
01 12 01 03 80 a0 5a 78 0a 0d c9 a0 57 47 98 27
12 48 4c 21 08 00 81 80 01 01 01 01 01 01 01 01
01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
45 00 40 84 63 00 00 1e 01 1d 00 72 51 d0 1e 20
6e 28 55 00 40 84 63 00 00 1e 00 00 00 fc 00 53
4f 4e 59 20 54 56 20 58 56 0a 20 20 00 00 00 fd
00 30 3e 0e 46 0f 00 0a 20 20 20 20 20 20 01 e402 03 2b 70 50 1f 10 14 05 13 04 12 11 16 15 03
02 07 06 01 20 23 09 07 07 83 01 00 00 66 03 0c
00 20 00 80 e3 05 03 01 e2 00 39 02 3a 80 d0 72
38 2d 40 10 2c 45 80 40 84 63 00 00 1e 01 1d 00
bc 52 d0 1e 20 b8 28 55 40 40 84 63 00 00 1e 01
1d 80 18 71 1c 16 20 58 2c 25 00 40 84 63 00 00
9e 01 1d 80 d0 72 1c 16 20 10 2c 25 80 40 84 63
00 00 9e 00 00 00 00 00 00 00 00 00 00 00 00 ba----------------
Block 0, Base EDID:
EDID Structure Version & Revision: 1.3
Vendor & Product Identification:
Manufacturer: SNY
Model: 23553
Serial Number: 16843009
Made in: week 1 of 2008
Basic Display Parameters & Features:
Digital display
Maximum image size: 160 cm x 90 cm
Gamma: 2.20
RGB color display
First detailed timing is the preferred timing
Color Characteristics:
Red : 0.6250, 0.3398
Green: 0.2802, 0.5947
Blue : 0.1552, 0.0703
White: 0.2832, 0.2978
Established Timings I & II:
DMT 0x04: 640x480 59.940 Hz 4:3 31.469 kHz 25.175 MHz
DMT 0x09: 800x600 60.317 Hz 4:3 37.879 kHz 40.000 MHz
DMT 0x10: 1024x768 60.004 Hz 4:3 48.363 kHz 65.000 MHz
Standard Timings:
DMT 0x23: 1280x1024 60.020 Hz 5:4 63.981 kHz 108.000 MHz
Detailed Timing Descriptors:
DTD 1: 1920x1080 60.000 Hz 16:9 67.500 kHz 148.500 MHz (1600 mm x 900 mm)
Hfront 88 Hsync 44 Hback 148 Hpol P
Vfront 4 Vsync 5 Vback 36 Vpol P
DTD 2: 1280x720 60.000 Hz 16:9 45.000 kHz 74.250 MHz (1600 mm x 900 mm)
Hfront 110 Hsync 40 Hback 220 Hpol P
Vfront 5 Vsync 5 Vback 20 Vpol P
Display Product Name: 'SONY TV XV'
Display Range Limits:
Monitor ranges (GTF): 48-62 Hz V, 14-70 kHz H, max dotclock 150 MHz
Extension blocks: 1
Checksum: 0xe4----------------
Block 1, CTA-861 Extension Block:
Revision: 3
Basic audio support
Supports YCbCr 4:4:4
Supports YCbCr 4:2:2
Native detailed modes: 0
Video Data Block:
VIC 31: 1920x1080 50.000 Hz 16:9 56.250 kHz 148.500 MHz
VIC 16: 1920x1080 60.000 Hz 16:9 67.500 kHz 148.500 MHz
VIC 20: 1920x1080i 50.000 Hz 16:9 28.125 kHz 74.250 MHz
VIC 5: 1920x1080i 60.000 Hz 16:9 33.750 kHz 74.250 MHz
VIC 19: 1280x720 50.000 Hz 16:9 37.500 kHz 74.250 MHz
VIC 4: 1280x720 60.000 Hz 16:9 45.000 kHz 74.250 MHz
VIC 18: 720x576 50.000 Hz 16:9 31.250 kHz 27.000 MHz
VIC 17: 720x576 50.000 Hz 4:3 31.250 kHz 27.000 MHz
VIC 22: 1440x576i 50.000 Hz 16:9 15.625 kHz 27.000 MHz
VIC 21: 1440x576i 50.000 Hz 4:3 15.625 kHz 27.000 MHz
VIC 3: 720x480 59.940 Hz 16:9 31.469 kHz 27.000 MHz
VIC 2: 720x480 59.940 Hz 4:3 31.469 kHz 27.000 MHz
VIC 7: 1440x480i 59.940 Hz 16:9 15.734 kHz 27.000 MHz
VIC 6: 1440x480i 59.940 Hz 4:3 15.734 kHz 27.000 MHz
VIC 1: 640x480 59.940 Hz 4:3 31.469 kHz 25.175 MHz
VIC 32: 1920x1080 24.000 Hz 16:9 27.000 kHz 74.250 MHz
Audio Data Block:
Linear PCM:
Max channels: 2
Supported sample rates (kHz): 48 44.1 32
Supported sample sizes (bits): 24 20 16
Speaker Allocation Data Block:
FL/FR - Front Left/Right
Vendor-Specific Data Block (HDMI), OUI 00-0C-03:
Source physical address: 2.0.0.0
Supports_AI
Colorimetry Data Block:
xvYCC601
xvYCC709
Video Capability Data Block:
YCbCr quantization: No Data
RGB quantization: No Data
PT scan behavior: Supports both over- and underscan
IT scan behavior: Always Underscanned
CE scan behavior: Always Overscanned
Detailed Timing Descriptors:
DTD 3: 1920x1080 50.000 Hz 16:9 56.250 kHz 148.500 MHz (1600 mm x 900 mm)
Hfront 528 Hsync 44 Hback 148 Hpol P
Vfront 4 Vsync 5 Vback 36 Vpol P
DTD 4: 1280x720 50.000 Hz 16:9 37.500 kHz 74.250 MHz (1600 mm x 900 mm)
Hfront 440 Hsync 40 Hback 220 Hpol P
Vfront 5 Vsync 5 Vback 20 Vpol P
DTD 5: 1920x1080i 60.000 Hz 16:9 33.750 kHz 74.250 MHz (1600 mm x 900 mm)
Hfront 88 Hsync 44 Hback 148 Hpol P
Vfront 2 Vsync 5 Vback 15 Vpol P Vfront +0.5 Odd Field
Vfront 2 Vsync 5 Vback 15 Vpol P Vback +0.5 Even Field
DTD 6: 1920x1080i 50.000 Hz 16:9 28.125 kHz 74.250 MHz (1600 mm x 900 mm)
Hfront 528 Hsync 44 Hback 148 Hpol P
Vfront 2 Vsync 5 Vback 15 Vpol P Vfront +0.5 Odd Field
Vfront 2 Vsync 5 Vback 15 Vpol P Vback +0.5 Even Field
Checksum: 0xba
joanxie
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I mean that you dump the clk_summary.
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Hi,
sorry for my late reply. Here is the clock dump, when connected to my 1920x1080 tv:
cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
dummy 0 0 0 0 0 0 50000
sai7_mclk 0 0 0 0 0 0 50000
sai6_mclk 0 0 0 0 0 0 50000
sai5_mclk 0 0 0 0 0 0 50000
sai3_mclk 0 0 0 0 0 0 50000
sai2_mclk 0 0 0 0 0 0 50000
sai1_mclk 0 0 0 0 0 0 50000
clk_ext4 0 0 0 133000000 0 0 50000
clk_ext3 0 0 0 133000000 0 0 50000
clk_ext2 0 0 0 133000000 0 0 50000
clk_ext1 0 0 0 133000000 0 0 50000
osc_24m 13 13 0 24000000 0 0 50000
aud_pll_clk 0 0 0 24000000 0 0 50000
sai_pll_ref_sel 0 0 0 24000000 0 0 50000
sai_pll 0 0 0 49152000 0 0 50000
sai_pll_bypass 0 0 0 49152000 0 0 50000
sai_pll_out 0 0 0 49152000 0 0 50000
earc_phy_clk 0 0 0 49152000 0 0 50000
sai7_mclk3_clk 0 0 0 49152000 0 0 50000
sai6_mclk3_clk 0 0 0 49152000 0 0 50000
sai5_mclk3_clk 0 0 0 49152000 0 0 50000
sai3_mclk3_clk 0 0 0 49152000 0 0 50000
sai2_mclk3_clk 0 0 0 49152000 0 0 50000
sai1_mclk3_clk 0 0 0 49152000 0 0 50000
usb_phy_ref 1 1 0 24000000 0 0 50000
usb_phy_root_clk 2 2 0 24000000 0 0 50000
sai7 0 0 0 24000000 0 0 50000
sai7_root 0 0 0 24000000 0 0 50000
sai7_mclk1_sel 0 0 0 24000000 0 0 50000
sai7_mclk1_clk 0 0 0 24000000 0 0 50000
pdm 0 0 0 24000000 0 0 50000
pdm_root 0 0 0 24000000 0 0 50000
pdm_sel 0 0 0 24000000 0 0 50000
pdm_root_clk 0 0 0 24000000 0 0 50000
media_mipi_test_byte 0 0 0 24000000 0 0 50000
pcie2_phy 0 0 0 24000000 0 0 50000
pcie2_ctrl 0 0 0 24000000 0 0 50000
mem_repair 1 1 0 24000000 0 0 50000
media_ldb 0 0 0 24000000 0 0 50000
media_ldb_root_clk 0 0 0 24000000 0 0 50000
media_disp1_pix 0 0 0 24000000 0 0 50000
media_disp1_pix_root_clk 0 0 0 24000000 0 0 50000
lcdif_pixel_clk 0 0 0 24000000 0 0 50000
hdmi_ref_266m 1 1 0 24000000 0 0 50000
hdmi_glb_ref_266m 0 0 0 24000000 0 0 50000
hdmi_sec_mem 0 0 0 24000000 0 0 50000
hdmi_esm 0 0 0 24000000 0 0 50000
hdmi_24m 2 2 0 24000000 0 0 50000
hdmi_glb_24m 2 2 0 24000000 0 0 50000
hdmi_phy 2 2 0 0 0 0 50000
hdmi_glb_pix 5 5 0 0 0 0 50000
hdmi_pipe_sel 1 1 0 0 0 0 50000
lcdif_clk_sel 0 0 0 0 0 0 50000
hdmi_vid_pix 1 1 0 0 0 0 50000
hdmi_tx_pix 1 1 0 0 0 0 50000
lcdif3_pxl 1 1 0 0 0 0 50000
hdmi_phy_sel 0 0 0 24000000 0 0 50000
hdmi_fdcc_tst 1 1 0 24000000 0 0 50000
hdmi_fdcc_ref 1 1 0 24000000 0 0 50000
ipp_do_clko2 0 0 0 24000000 0 0 50000
ipp_do_clko1 0 0 0 24000000 0 0 50000
wdog 1 1 0 24000000 0 0 50000
wdog3_root_clk 0 0 0 24000000 0 0 50000
wdog2_root_clk 0 0 0 24000000 0 0 50000
wdog1_root_clk 1 1 0 24000000 0 0 50000
gpt6 0 0 0 24000000 0 0 50000
gpt6_root_clk 0 0 0 24000000 0 0 50000
gpt5 0 0 0 24000000 0 0 50000
gpt5_root_clk 0 0 0 24000000 0 0 50000
gpt4 0 0 0 24000000 0 0 50000
gpt4_root_clk 0 0 0 24000000 0 0 50000
gpt3 0 0 0 24000000 0 0 50000
gpt3_root_clk 0 0 0 24000000 0 0 50000
gpt2 0 0 0 24000000 0 0 50000
gpt2_root_clk 0 0 0 24000000 0 0 50000
gpt1 0 0 0 24000000 0 0 50000
gpt1_root_clk 0 0 0 24000000 0 0 50000
pwm4 0 0 0 24000000 0 0 50000
pwm4_root_clk 0 0 0 24000000 0 0 50000
pwm3 0 0 0 24000000 0 0 50000
pwm3_root_clk 0 0 0 24000000 0 0 50000
pwm2 0 0 0 24000000 0 0 50000
pwm2_root_clk 0 0 0 24000000 0 0 50000
pwm1 0 0 0 24000000 0 0 50000
pwm1_root_clk 0 0 0 24000000 0 0 50000
usb_core_ref 2 2 0 24000000 0 0 50000
uart4 0 0 0 24000000 0 0 50000
uart4_root_clk 0 0 0 24000000 0 0 50000
uart3 0 0 0 24000000 0 0 50000
uart3_root_clk 0 0 0 24000000 0 0 50000
uart2 1 1 0 24000000 0 0 50000
uart2_root_clk 4 4 0 24000000 0 0 50000
i2c4 0 0 0 24000000 0 0 50000
i2c4_root_clk 0 0 0 24000000 0 0 50000
i2c3 0 0 0 24000000 0 0 50000
i2c3_root_clk 0 0 0 24000000 0 0 50000
i2c2 0 0 0 24000000 0 0 50000
i2c2_root_clk 0 0 0 24000000 0 0 50000
i2c1 0 0 0 24000000 0 0 50000
i2c1_root_clk 0 0 0 24000000 0 0 50000
enet_phy_ref 0 0 0 24000000 0 0 50000
sai6 0 0 0 24000000 0 0 50000
sai6_root 0 0 0 24000000 0 0 50000
sai6_mclk1_sel 0 0 0 24000000 0 0 50000
sai6_mclk1_clk 0 0 0 24000000 0 0 50000
sai5 0 0 0 24000000 0 0 50000
sai5_root 0 0 0 24000000 0 0 50000
sai5_mclk1_sel 0 0 0 24000000 0 0 50000
sai5_mclk1_clk 0 0 0 24000000 0 0 50000
sai4 0 0 0 24000000 0 0 50000
sai2 0 0 0 24000000 0 0 50000
sai2_root 0 0 0 24000000 0 0 50000
sai2_mclk1_sel 0 0 0 24000000 0 0 50000
sai2_mclk1_clk 0 0 0 24000000 0 0 50000
sai1 0 0 0 24000000 0 0 50000
sai1_root 0 0 0 24000000 0 0 50000
sai7_mclk2_sel 0 0 0 24000000 0 0 50000
sai7_mclk2_clk 0 0 0 24000000 0 0 50000
sai6_mclk2_sel 0 0 0 24000000 0 0 50000
sai6_mclk2_clk 0 0 0 24000000 0 0 50000
sai5_mclk2_sel 0 0 0 24000000 0 0 50000
sai5_mclk2_clk 0 0 0 24000000 0 0 50000
sai3_mclk2_sel 0 0 0 24000000 0 0 50000
sai3_mclk2_clk 0 0 0 24000000 0 0 50000
sai2_mclk2_sel 0 0 0 24000000 0 0 50000
sai2_mclk2_clk 0 0 0 24000000 0 0 50000
sai1_mclk2_sel 0 0 0 24000000 0 0 50000
sai1_mclk2_clk 0 0 0 24000000 0 0 50000
sai1_mclk1_sel 0 0 0 24000000 0 0 50000
sai1_mclk1_clk 0 0 0 24000000 0 0 50000
i2c6 0 0 0 24000000 0 0 50000
i2c6_root_clk 0 0 0 24000000 0 0 50000
i2c5 0 0 0 24000000 0 0 50000
i2c5_root_clk 0 0 0 24000000 0 0 50000
pcie_aux 0 0 0 24000000 0 0 50000
pcie_root_clk 0 0 0 24000000 0 0 50000
mipi_dsi_esc_rx 0 0 0 24000000 0 0 50000
media_isp 0 0 0 24000000 0 0 50000
media_isp_root_clk 0 0 0 24000000 0 0 50000
isp_cor_clk 0 0 0 24000000 0 0 50000
sys_pll3_ref_sel 0 0 0 24000000 0 0 50000
sys_pll3 0 0 0 600000000 0 0 50000
sys_pll3_bypass 0 0 0 600000000 0 0 50000
sys_pll3_out 0 0 0 600000000 0 0 50000
sys_pll2_ref_sel 1 1 0 24000000 0 0 50000
sys_pll2 1 1 0 1000000000 0 0 50000
sys_pll2_bypass 1 1 0 1000000000 0 0 50000
sys_pll2_out 4 4 0 1000000000 0 0 50000
sys_pll2_1000m 1 1 0 1000000000 0 0 50000
vpu_vc8000e 0 0 0 500000000 0 0 50000
vpu_vc8ke_root_clk 0 0 0 500000000 0 0 50000
ml_core 0 0 0 1000000000 0 0 50000
npu_root_clk 0 0 0 1000000000 0 0 50000
gpu2d_core 0 0 0 1000000000 0 0 50000
gpu2d_root_clk 0 0 0 1000000000 0 0 50000
gpu3d_shader_core 0 0 0 1000000000 0 0 50000
gpu3d_core 0 0 0 1000000000 0 0 50000
gpu3d_root_clk 0 0 0 1000000000 0 0 50000
media_cam1_pix 0 0 0 500000000 0 0 50000
media_cam1_pix_root_clk 0 0 0 500000000 0 0 50000
mipi_csi_aclk 0 0 0 500000000 0 0 50000
media_axi 0 0 0 500000000 0 0 50000
media_axi_root_clk 0 0 0 500000000 0 0 50000
lcdif2_axi_clk 0 0 0 500000000 0 0 50000
lcdif_axi_clk 0 0 0 500000000 0 0 50000
dwe_axi_clk 0 0 0 500000000 0 0 50000
dwe_cor_clk 0 0 0 500000000 0 0 50000
isp_axi_clk 0 0 0 500000000 0 0 50000
isi_proc_clk 0 0 0 500000000 0 0 50000
noc 1 1 0 1000000000 0 0 50000
sys_pll2_500m 3 3 0 500000000 0 0 50000
hsio_axi 2 2 0 500000000 0 0 50000
hdmi_axi 3 3 0 500000000 0 0 50000
hdmi_glb_b 2 2 0 500000000 0 0 50000
lcdif3_b 1 1 0 500000000 0 0 50000
hdmi_root_clk 1 1 0 500000000 0 0 50000
gic 1 1 0 500000000 0 0 50000
nand 0 0 0 500000000 0 0 50000
nand_root_clk 0 0 0 500000000 0 0 50000
sys_pll2_333m 0 0 0 333333333 0 0 50000
sys_pll2_250m 0 0 0 250000000 0 0 50000
sys_pll2_200m 0 0 0 200000000 0 0 50000
ecspi3 0 0 0 50000000 0 0 50000
ecspi3_root_clk 0 0 0 50000000 0 0 50000
ecspi2 0 0 0 50000000 0 0 50000
ecspi2_root_clk 0 0 0 50000000 0 0 50000
ecspi1 0 0 0 50000000 0 0 50000
ecspi1_root_clk 0 0 0 50000000 0 0 50000
m7_core 0 0 0 200000000 0 0 50000
sys_pll2_166m 0 0 0 166666666 0 0 50000
sys_pll2_125m 1 1 0 125000000 0 0 50000
enet_qos 1 1 0 125000000 0 0 50000
sys_pll2_100m 1 1 0 100000000 0 0 50000
enet_timer 0 0 0 25000000 0 0 50000
enet_qos_timer 1 1 0 100000000 0 0 50000
sys_pll2_50m 0 0 0 50000000 0 0 50000
enet_ref 0 0 0 50000000 0 0 50000
sys_pll1_ref_sel 1 1 0 24000000 0 0 50000
sys_pll1 1 1 0 800000000 0 0 50000
sys_pll1_bypass 1 1 0 800000000 0 0 50000
sys_pll1_out 3 3 0 800000000 0 0 50000
sys_pll1_800m 3 4 0 800000000 0 0 50000
vpu_bus 0 0 0 800000000 0 0 50000
vpu_root_clk 0 0 0 800000000 0 0 50000
vpu_g1 0 0 0 800000000 0 0 50000
vpu_g1_root_clk 0 0 0 800000000 0 0 50000
ml_ahb 0 0 0 400000000 0 0 50000
ml_axi 0 0 0 800000000 0 0 50000
gpu_ahb 0 0 0 400000000 0 0 50000
gpu_axi 0 0 0 800000000 0 0 50000
gpu_root_clk 0 0 0 800000000 0 0 50000
audio_axi 0 0 0 800000000 0 0 50000
audio_axi_root 0 0 0 800000000 0 0 50000
ocram_a_ipg_clk 0 0 0 800000000 0 0 50000
dsp_dbg_clk 0 0 0 800000000 0 0 50000
dsp_root_clk 0 0 0 800000000 0 0 50000
audio_ahb 0 1 0 400000000 0 0 50000
audio_ahb_root 0 2 0 400000000 0 0 50000
mu3_root_clk 0 0 0 400000000 0 0 50000
mu2_root_clk 0 0 0 400000000 0 0 50000
edma_root_clk 0 0 0 400000000 0 0 50000
aud2htx_ipg_clk 0 0 0 400000000 0 0 50000
earc_ipg_clk 0 0 0 400000000 0 0 50000
spba2_root_clk 0 0 0 400000000 0 0 50000
sdma3_root_clk 0 0 0 400000000 0 0 50000
pdm_ipg_clk 0 0 0 400000000 0 0 50000
asrc_ipg_clk 0 0 0 400000000 0 0 50000
sai7_ipg_clk 0 0 0 400000000 0 0 50000
sai6_ipg_clk 0 0 0 400000000 0 0 50000
sai5_ipg_clk 0 0 0 400000000 0 0 50000
sai3_ipg_clk 0 0 0 400000000 0 0 50000
sai2_ipg_clk 0 0 0 400000000 0 0 50000
sai1_ipg_clk 0 0 0 400000000 0 0 50000
noc_io 1 1 0 800000000 0 0 50000
arm_a53_div 0 0 0 800000000 0 0 50000
dram_apb 1 1 0 160000000 0 0 50000
media_apb 0 0 0 200000000 0 0 50000
media_apb_root_clk 0 0 0 200000000 0 0 50000
dwe_ahb_clk 0 0 0 200000000 0 0 50000
isp_ahb_clk 0 0 0 200000000 0 0 50000
lcdif2_apb_clk 0 0 0 200000000 0 0 50000
mipi_csi2_pclk 0 0 0 200000000 0 0 50000
isi_apb_clk 0 0 0 200000000 0 0 50000
lcdif_apb_clk 0 0 0 200000000 0 0 50000
mipi_csi_pclk 0 0 0 200000000 0 0 50000
mipi_dsi_pclk 0 0 0 200000000 0 0 50000
main_axi 1 1 0 400000000 0 0 50000
sys_pll1_400m 0 0 0 400000000 0 0 50000
usdhc3 0 0 0 400000000 0 0 50000
usdhc3_root_clk 0 0 0 400000000 0 0 50000
usdhc2 0 0 0 400000000 0 0 50000
usdhc2_root_clk 0 0 0 400000000 0 0 50000
usdhc1 0 0 0 200000000 0 0 50000
usdhc1_root_clk 0 0 0 200000000 0 0 50000
qspi 0 0 0 400000000 0 0 50000
qspi_root_clk 0 0 0 400000000 0 0 50000
sys_pll1_266m 1 1 0 266666666 0 0 50000
media_cam2_pix 0 0 0 266666666 0 0 50000
media_cam2_pix_root_clk 0 0 0 266666666 0 0 50000
mipi_csi2_aclk 0 0 0 266666666 0 0 50000
nand_usdhc_bus 0 0 0 266666666 0 0 50000
nand_usdhc_rawnand_clk 0 0 0 266666666 0 0 50000
enet_axi 1 1 0 266666666 0 0 50000
sim_enet_root_clk 1 1 0 266666666 0 0 50000
enet_qos_root_clk 1 1 0 266666666 0 0 50000
enet1_root_clk 0 0 0 266666666 0 0 50000
sys_pll1_200m 0 0 0 200000000 0 0 50000
sys_pll1_160m 0 0 0 160000000 0 0 50000
can2 0 0 0 80000000 0 0 50000
can2_root_clk 0 0 0 80000000 0 0 50000
can1 0 0 0 80000000 0 0 50000
can1_root_clk 0 0 0 80000000 0 0 50000
sys_pll1_133m 2 2 0 133333333 0 0 50000
hdmi_apb 4 4 0 133333333 0 0 50000
hdmi_glb_apb 14 14 0 133333333 0 0 50000
hdmi_trng_apb 0 0 0 133333333 0 0 50000
hdmi_trng_skp 0 0 0 133333333 0 0 50000
hdmi_phy_int 1 1 0 133333333 0 0 50000
hdmi_phy_apb 1 1 0 133333333 0 0 50000
hdmi_tx_prep 1 1 0 133333333 0 0 50000
hdmi_tx_skp 1 1 0 133333333 0 0 50000
hdmi_tx_sfr 1 1 0 133333333 0 0 50000
hdmi_tx_gpa 1 1 0 133333333 0 0 50000
hdmi_tx_apb 1 1 0 133333333 0 0 50000
hdmi_tx_hpi 1 1 0 133333333 0 0 50000
vsfd_cea 0 0 0 133333333 0 0 50000
hrv_mwr_cea 0 0 0 133333333 0 0 50000
hrv_mwr_apb 0 0 0 133333333 0 0 50000
lcdif3_spu 1 1 0 133333333 0 0 50000
lcdif3_pdi 1 1 0 133333333 0 0 50000
lcdif3_apb 1 1 0 133333333 0 0 50000
hdcp_noc 0 0 0 133333333 0 0 50000
hdmi_noc 1 1 0 133333333 0 0 50000
hdmi_irq_steer 1 1 0 133333333 0 0 50000
ahb_root 3 3 0 133333333 0 0 50000
ipg_root 9 9 0 66666667 0 0 50000
tsensor_root_clk 1 1 0 66666667 0 0 50000
hsio_root_clk 2 2 0 66666667 0 0 50000
snvs_root_clk 2 2 0 66666667 0 0 50000
sdma1_root_clk 1 1 0 66666667 0 0 50000
qos_enet_root_clk 1 1 0 66666667 0 0 50000
qos_root_clk 0 0 0 66666667 0 0 50000
ocotp_root_clk 0 0 0 66666667 0 0 50000
mu_root_clk 0 0 0 66666667 0 0 50000
gpio5_root_clk 0 0 0 66666667 0 0 50000
gpio4_root_clk 1 1 0 66666667 0 0 50000
gpio3_root_clk 1 1 0 66666667 0 0 50000
gpio2_root_clk 1 1 0 66666667 0 0 50000
gpio1_root_clk 1 1 0 66666667 0 0 50000
sys_pll1_100m 0 0 0 100000000 0 0 50000
dram_alt 0 0 0 100000000 0 0 50000
dram_alt_root 0 0 0 25000000 0 0 50000
sys_pll1_80m 0 0 0 80000000 0 0 50000
uart1 0 0 0 80000000 0 0 50000
uart1_root_clk 0 0 0 80000000 0 0 50000
sys_pll1_40m 0 0 0 40000000 0 0 50000
wrclk 0 0 0 40000000 0 0 50000
arm_pll_ref_sel 1 1 0 24000000 0 0 50000
arm_pll 1 1 0 1200000000 0 0 50000
arm_pll_bypass 1 1 0 1200000000 0 0 50000
arm_pll_out 1 1 0 1200000000 0 0 50000
arm_a53_core 1 1 0 1200000000 0 0 50000
arm 1 1 0 1200000000 0 0 50000
vpu_pll_ref_sel 0 0 0 24000000 0 0 50000
vpu_pll 0 0 0 700000000 0 0 50000
vpu_pll_bypass 0 0 0 700000000 0 0 50000
vpu_pll_out 0 0 0 700000000 0 0 50000
vpu_g2 0 0 0 700000000 0 0 50000
vpu_g2_root_clk 0 0 0 700000000 0 0 50000
gpu_pll_ref_sel 0 0 0 24000000 0 0 50000
gpu_pll 0 0 0 1000000000 0 0 50000
gpu_pll_bypass 0 0 0 1000000000 0 0 50000
gpu_pll_out 0 0 0 1000000000 0 0 50000
dram_pll_ref_sel 1 1 0 24000000 0 0 50000
dram_pll 1 1 0 1000000000 0 0 50000
dram_pll_bypass 1 1 0 1000000000 0 0 50000
dram_pll_out 1 1 0 1000000000 0 0 50000
dram_core_clk 2 2 0 1000000000 0 0 50000
dram1_root_clk 1 1 0 1000000000 0 0 50000
video_pll1_ref_sel 0 0 0 24000000 0 0 50000
video_pll1 0 0 0 1039500000 0 0 50000
video_pll1_bypass 0 0 0 1039500000 0 0 50000
video_pll1_out 0 0 0 1039500000 0 0 50000
media_disp2_pix 0 0 0 1039500000 0 0 50000
media_disp2_pix_root_clk 0 0 0 1039500000 0 0 50000
lcdif2_pixel_clk 0 0 0 1039500000 0 0 50000
media_mipi_phy1_ref 0 0 0 47250000 0 0 50000
mipi_dsi2_clk 0 0 0 47250000 0 0 50000
mipi_dsi_clkref 0 0 0 47250000 0 0 50000
audio_pll2_ref_sel 0 0 0 24000000 0 0 50000
audio_pll2 0 0 0 361267200 0 0 50000
audio_pll2_bypass 0 0 0 361267200 0 0 50000
audio_pll2_out 0 0 0 361267200 0 0 50000
audio_pll1_ref_sel 0 0 0 24000000 0 0 50000
audio_pll1 0 0 0 393216000 0 0 50000
audio_pll1_bypass 0 0 0 393216000 0 0 50000
audio_pll1_out 0 0 0 393216000 0 0 50000
sai3 0 0 0 393216000 0 0 50000
sai3_root 0 0 0 393216000 0 0 50000
sai3_mclk1_sel 0 0 0 393216000 0 0 50000
sai3_mclk1_clk 0 0 0 393216000 0 0 50000
osc_32k 2 2 0 32768 0 0 50000
hdmi_glb_32k 1 1 0 32768 0 0 50000
hdmi_cec 1 1 0 32768 0 0 50000
usb_root_clk 4 4 0 32768 0 0 50000
hrv_mwr_b 0 0 0 0 0 0 50000
/sys/devices/platform/display-subsystem/graphics/fb0 # cat /sys/kernel/debug/clk
/clk_summary | grep "hdmi"
hdmi_ref_266m 1 1 0 24000000 0 0 50000
hdmi_glb_ref_266m 0 0 0 24000000 0 0 50000
hdmi_sec_mem 0 0 0 24000000 0 0 50000
hdmi_esm 0 0 0 24000000 0 0 50000
hdmi_24m 2 2 0 24000000 0 0 50000
hdmi_glb_24m 2 2 0 24000000 0 0 50000
hdmi_phy 2 2 0 0 0 0 50000
hdmi_glb_pix 5 5 0 0 0 0 50000
hdmi_pipe_sel 1 1 0 0 0 0 50000
hdmi_vid_pix 1 1 0 0 0 0 50000
hdmi_tx_pix 1 1 0 0 0 0 50000
hdmi_phy_sel 0 0 0 24000000 0 0 50000
hdmi_fdcc_tst 1 1 0 24000000 0 0 50000
hdmi_fdcc_ref 1 1 0 24000000 0 0 50000
hdmi_axi 3 3 0 500000000 0 0 50000
hdmi_glb_b 2 2 0 500000000 0 0 50000
hdmi_root_clk 1 1 0 500000000 0 0 50000
hdmi_apb 4 4 0 133333333 0 0 50000
hdmi_glb_apb 14 14 0 133333333 0 0 50000
hdmi_trng_apb 0 0 0 133333333 0 0 50000
hdmi_trng_skp 0 0 0 133333333 0 0 50000
hdmi_phy_int 1 1 0 133333333 0 0 50000
hdmi_phy_apb 1 1 0 133333333 0 0 50000
hdmi_tx_prep 1 1 0 133333333 0 0 50000
hdmi_tx_skp 1 1 0 133333333 0 0 50000
hdmi_tx_sfr 1 1 0 133333333 0 0 50000
hdmi_tx_gpa 1 1 0 133333333 0 0 50000
hdmi_tx_apb 1 1 0 133333333 0 0 50000
hdmi_tx_hpi 1 1 0 133333333 0 0 50000
hdmi_noc 1 1 0 133333333 0 0 50000
hdmi_irq_steer 1 1 0 133333333 0 0 50000
hdmi_glb_32k 1 1 0 32768 0 0 50000
hdmi_cec 1 1 0 32768 0 0 50000
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I finally have a solution. The problem was in hardware. We used an older HDMI Port Protection and Interface chip which only supported HDMI 1.3 after removing this chip and connecting the wires directly, the HDMI output worked.
