i.MX6D LVDSx_CLK_ SEL

[sugiyamatoshihi]

Hi, 

There is the register LVDS1_CLK_SEL and LVDS2_CLK_SEL in CCM_ANALOG_MISC1n. How to chose the clock by these selector?

 It is not clear where to connect.  What is the anaclk1/1b and anaclk 2/2b?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Igor,

Thanks for advice.

I 'd like to know LVDS1_CLK_SEL and LVDS2_CLK_SEL in CCM_ANALOG_MISC1n, too.

That explanation is "This field selects the clk to be routed to anaclk1/1b".

Does this means LVDS0_CLK_P input clock routed to CLK1_P and CLK1_N?

Best Regards,

Sugiyama

[igorpadykov · Accepted solution]

Hi Sugiama

>That explanation is "This field selects the clk to be routed to anaclk1/1b".

clock selected by LVDS1_CLK_SEL is routed to CLK1_P and CLK1_N.

Best regards
igor

[sugiyamatoshihi]

Hi, Igor,

I understood it.

Which is the source clock? I think CLK1_P/N are input.

If so, LVDS1_CLK_SEL chose source clock for CLK1_P/N.

Is it right?

It seems it doesn’t related the name of LVDS.

What case, this selector use?

Best Regards,

Sugiyama

[igorpadykov]

Hi Sugiyama

it can be input  (when LVDSCLK1_IBEN is set) and output (when LVDSCLK1_OBEN is set).

What do you mean by "Which is the source clock? ".

Best regards
igor

[sugiyamatoshihi]

Hi, Igor,

Thanks for support.

Now, I may understand.

anaclk1/1b and anaclk2/2b are output clock for CLK1_P/N and CLK2_P/N from clock selected by LVDSx_CLK_SEL. 

I wrote a diagram of clock route that attached. Is this correct, especially written in red?

Best Regards,

Sugiyama

[igorpadykov]

Hi Sugiyama

yes, diagram is correct.

Best regards
igor

[sugiyamatoshihi]

Hi, Igor,

I uderstand clearly.

Thanks a lot.

Best Regards,

Sugiyama

[igorpadykov]

Hi Sugiyama

anaclk1/1b and anaclk 2/2b are CLK1_P/CLK1_N and CLK2_P/CLK2_N

described on sect.4.1.1 Pin Assignments i.MX6DQ Reference Manual, also some details provided on

https://community.nxp.com/message/485772?commentID=485772#comment-485772 

Best regards
igor
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[sugiyamatoshihi]

Hi, Igor,

Thanks for information.

Does it means 'anaclk 1/1b' are Pad name CLK1_N/P as signal XTALOSC_CLK1_N/P? 

It seems PLL bypass clock.  

I don't have a permission to see485772 .

Could you explain detail?

Best Regards,

Sugiyama

[igorpadykov]

Hi Sugiama

anaclk1 is CLK1_P and CLK1_N is anaclk1b.

There are no much details on thread, just name explanation.

You can create service request to obtain copy of web page.

Best regards
igor