i.MX6 SoloX RGMII signal timing original and internal delay

[m_c]

In page 94 i.MX6 SoloX data sheet <http://www.freescale.com/files/32bit/doc/data_sheet/IMX6SXAEC.pdf>, there are figure 55 & 56 shows timing original and internal delay. May we know how to change this timing mode?

[igorpadykov · Accepted solution]

Hi mc

note, figure 55 & 56 are the same as 54,55 IMX6DQCEC (rev.4,7/2015).pdf.

The i.MX6 Datasheet(s) do not provide the setup and hold timings, assuming using

the delay parameters. RGMII specs allow implementation of a delay on TXC or RXC

inside a transmitter.

To operate correctly :

TskewT max of MAC should be less than TskewR min of PHY.

TskewT max of PHY should be less than TskewR min of MAC.

Next, according to the i.MX6 Datasheet :

PC board design will require clocks to be routed such that an additional trace

delay of greater than 1.2 ns and less than 1.7 ns will be added to the

associated clock signal.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------