i.MX6 Dual in 32-bit DDR3 configuration

[rafaeldelrey]

Hello,

I need to redesign an i.MX6 Dual design, pursuing to lower costs with only 2 DDR3 ICs instead of 4 in the original design.

Due to cost reasons (my main target), this is cheaper than jumping to LP-DDR2 memories.

Also due to SW reasons, as far as I know, I need to stick to i.MX6 Dual device.

The question is: Can I leave DQ[32-64] and their respective DQS signals disconnected in order to use a true 32-bit memory bus in the i.MX6 Dual? or they (DQ[32-64]) should be terminated somehow (33 to 50 ohms Pullup or pulldown or whatever)?

Thanks

[gusarambula]

Hello Rafael del Rey,

Please look at the threads suggested by Jan for more details. Unused pins of the DDR controller may be left floating if not used.

Regards,

[jan_spurek · Accepted solution]

Hello Rafael,

please refer to the following threads:

https://community.nxp.com/message/591423

https://community.nxp.com/message/500229

Best Regards,
Jan