i.MX53 ESDCTL_SDCTRL register setting

[torus1000]

Hi

Now we are debugging LPDDR2 timing for our custom i.MX53 board.
  (Please see our previous thread : https://community.freescale.com/message/533008)

We tried to change ESDCTL_SDCTRL for adjust delay of SDCLK.
For the bit11-8 field description on p1298 of RM shows as following: "Add sdclk0 delay of 1 delay units."

(Q1) How many [pSec] does 1 delay units mean?
(Q2) Does more/bigger delay improve timing margin to the CS/RAS/CAS/WE/<adr>/<dat> of DDR2 read?

When we write 0x00000300(SDclk0_del=2'b11) to the ESDCTL_SDCTRL with JTAG-ICE, but read value was 0x00018000.

(Q3) What was wrong with my writing?

Best Regards.

[igorpadykov · Accepted solution]

Hi torus1000

1. 1 delay unit varies between 20 pSec in best case to 50 in worst case

2. yes

3. had you provided clocks to ESDCTL, is access provided as 32bit word ?

Please try to reproduce this on Freescale reference board, QuickStart board with

debugger tool which is used in Freescale - ARM RealView ICE. One can follow

Chapter 9 Configuring JTAG Tools for Debugging MX53UG

Best regards

igor

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