Hi all,
I am trying DDR stress test application by freescale on imx53.
I have custom board with following specs:
1GHz processor freq
400 GHz DDR freq
2 DDR3 chips with 128 MB each (total 256MB)
Previously I tried DDR stress test with input as:
1 DDR3 chip of 256 MB. In which DDR stress test is running fine.
But later I changed this to actual configuration (that is : 2 DDR
chips of 128 MB each) in which DDR stress test is failing.
Please help me to understand the problem.
Is there any particular changes needed in code/.inc file?
Thanks.
With regards,
Keshava
Hello. i am runing IMX536 With Mircon DDR3 MT41K256M16 ¨C 32 Meg x 16 x 8 banks DDR3 test. i download the inc file(the inc file name is MX53_TO2_DDR3_LCB_SMD_ARDb) from FSL.so i just modify the TRFC.TXS and some Parameters. run ddr test. the calibration is success. but the DDR test is fail. could you tell me whrer need to modify?
// Enable CSD0 and CSD1, row width = 15, column width = 10, burst length = 8, data width = 32bit
setmem /32 0x63fd9000 = 0xc3190000 //Main control register
// tRFC=208ck;tXS=68;tXP=3;tXPDLL=10;tFAW=24;CAS=4ck
setmem /32 0x63fd900C = 0x9f5152e3 //timing configuration Reg 0.
// tRCD=11;tRP=11;tRC=39;tRAS=28;tRPA=1;tWR=15;tMRD=4;tCWL=6ck
setmem /32 0x63fd9010 = 0xb68e8a63 //timing configuration Reg 1
// tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
setmem /32 0x63fd9014 = 0x01ff00db //timing configuration Reg 2
setmem /32 0x63fd902c = 0x000026d2 //command delay (default)
setmem /32 0x63fd9030 = 0x009f0e21 //out of reset delays
// Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
setmem /32 0x63fd9008 = 0x12273030 //ODT timings
// tCKE=5; tCKSRX=5; tCKSRE=5
setmem /32 0x63fd9004 = 0x0002002d //Power down control
Hi Yuri ,
Thanks for quick reply.
Actually we have only one hardware configuration. That is: "2 DDR chips of 128 MB each".
But due to misunderstanding, Initially, I used wrong input, i.e.: "1 DDR3 chip of 256 MB", for which stress test is working fine.
But, now it is not working for actual configuration, i.e.: "2 DDR chips of 128 MB each".
As of now, I don't have schematic, as it is customer board.
But customer confirmed that it is "2 DDR chips of 128 MB each".
Thanks again.
Regards,
Keshava
Hi Yuri,
Thanks for reply.
I asked with hardware team and it is confirmed that same CS is connected to both the DDRs.
Please advice...
Thanks & regards,
Keshava
From: Yuri Muhin
Sent: Wednesday, May 28, 2014 1:24 PM
To: Keshava G N
Subject: Re: - i.MX53 DDR3 stress test - Not working for correct configuration
i.MX53 DDR3 stress test - Not working for correct configuration
reply from Yuri Muhin in i.MX Community - View the full discussion
So, looks like, data port size has been changed between the two configurations :
- "1 DDR3 chip of 256 MB" ;
- "2 DDR chips of 128 MB each".
As result memory initialization should differ in port size. Is it so ?