I'm bringing up a custom i.MX283 based board. I'm having trouble with random lockups anywhere from 1 or 2 seconds to several minutes after applying power. I believe the issue is power related. I've implemented the design detailed in section 4.1.2.1 (VDD5V source only) of application note AN4199:
http://www.freescale.com/files/32bit/doc/app_note/AN4199.pdf
After researching the problem I came across this patch on the Freescale website:
Linux patch to add more robust support for a VDD5V or DCDC_BATT only
Currently, I'm using mainline kernel version 3.8.3 with u-boot version v2012.10.
Are the fixes described in the bootlet patch implemented in mainline u-boot? Can u-boot be configured for VDD5V only? I've looked into the u-boot and bootlet code, but the code is seemingly quite different...
Thanks,
Ryan
Solved! Go to Solution.
Hi Fabio,
The problem is u-boot's configuration of the low-level blocks of the power management unit in a 5V only scenario as defined in section 4.1.2 of the application note linked to in the original post. Late yesterday I was able to prove this by porting over the patched bootlet code into u-boot. It appears u-boot's SPL implementation is based on Freescale's original bootlet code. However, Freescale has released a 5V only patch to the bootlet code that has never made it into u-boot.
I now have a working system. Over time I'll try and clean up my modifications to u-boot and get some kind of patch together.
Thanks,
Ryan
In September I made some trials with Yocto. I've just run the evk with one of these images, core-image-minimal, and I see the same behaviour (U-boot 2014.01):
HTLLCL0x8050100b
HTLLCL0x8050100b
0x80502008
15 to 20 seconds gap
HTLLCLLC
U-Boot 2014.01 (Sep 26 2014 - 16:02:01)
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
DRAM: 128 MiB
NAND: 128 MiB
MMC: MXS MMC: 0
*** Warning - bad CRC, using default environment
I'm going to try 2014.10
Thanks,
Gonzalo.
Same behaviour using U-Boot 2014.10
HTLLCL0x8050100b
HTLLCL0x8050100b
0x80502008
HTLLCLLC
U-Boot 2014.10-dirty (Oct 17 2014 - 16:06:40)
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: SSP SD/MMC #0, 3V3
SPI: ready
DRAM: 128 MiB
NAND: 128 MiB
MMC: MXS MMC: 0
*** Warning - bad CRC, using default environment
Thanks,
Gonzalo
Boots fine here for me:
HTLLCLLC | ||
U-Boot 2014.10-rc1-16572-g080d72f (Aug 21 2014 - 18:13:55) | ||
CPU: Freescale i.MX28 rev1.2 at 454 MHz | ||
BOOT: SSP SD/MMC #0, 3V3 | ||
SPI: ready | ||
DRAM: 128 MiB | ||
NAND: 0 MiB | ||
MMC: MXS MMC: 0 | ||
Video: MXSFB: 'videomode' variable not set! | ||
In: | serial | |
Out: serial | ||
Err: serial | ||
Net: FEC0 [PRIME], FEC1 |
Hit any key to stop autoboot: 0
Fabio,
how is your switch S16 set up? can you try with S16 set to USB_5V?
Thanks,
Gonzalo.
S16 is at "Wall 5V". If I put it to "USB 5V" then it does not boot.
Thanks for your test. In my test, if S16 at
- Wall_5V: it works fine, as you've reported.
- USB_5V: You have to press the POWER button to start the board. The behaviour is the one described in my previous posts.
I think that S16 at USB_5V is the correct way to simulte operation under battery using mains supply instead of a battery. Do you agree?
Thanks,
Gonzalo.
If you are interested in powering the system with a battery you can connect a battery into J85 battery connector.
Hi Fabio,
no, I don't consider battery operation; my project (as this thread) is VDD5V source only.
But I found this issue with U-Boot and I didn't realized I had my evk in "battery source only". Hopefully, I haven't been able to reproduce the problem in VDD5V source only, so looks it's only related to battery operation.
Thanks for your support,
Gonzalo
Ok, got it. It seems things are working properly at your side then.
Ok, I can boot with S16 at USB 5V if I remove the wall power supply, then power the board via USB (J82) and set the S3 jumper to ON.
Hi Ryan, Are you using LTIB for your development? Also, Try to do your changes using the latest BSP (L2.6.35_1.1.0_130130).
Leo
I have more information about this issue. I've come to the conclusion that u-boot is broken for iMX28 designs that implement section 4.1.2.1 of AN4199 (see my first post for more info). If I apply the previously mentioned patch to the Freescale bootlet code I see a solid 1V8 rail on my DDR for instance, u-boot does not properly initialize the rail voltages in this configuration. Here's an oscope screen shot of the 1V8 when u-boot initializes the power supply...
I've modified u-boot/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c to force the iMX28 to use the 5V supply like the following but no luck (removed battery check and battery brown out initialization).
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
mxs_src_power_init();
/* 5V source detected, bad battery detected. */
writel(LRADC_CONVERSION_AUTOMATIC,
&lradc_regs->hw_lradc_conversion_clr);
clrbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BATT_VAL_MASK);
mxs_5v_boot();
mxs_power_clock2pll();
mxs_switch_vddd_to_dcdc_source();
}
If anyone has any suggestions as to how to fix this issue I'd be happy to try them.
Ryan,
Just to make sure I understand: if you apply the 5V patches into the bootlets code, and then launch the kernel via bootlets: you don't see any lockups in this case?
Fabio,
Yes, you are correct. More importantly though, if I apply the patch to the bootlet code I see a solid 1V8 on my DDR2 rail... the thrashing you see in the oscope screenshot above is gone.
Ryan