I've tried to find which peripheral bus (UART, SPI etc) controllers are connected via SPBA (Shared Peripheral Bus Arbiter) in Freescale documentation. There is no exact list in Reference manual. The only useful information is provided in IMX6DQRM.pdf. And this document is for iMX6 Q/DL chip. The "Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity" in SPBA section showing UART1, ECSPI1-5, AUDMUX, ESAI, SSI1-3, ASRC as peripherals connected to SPBA. This is 14 devices in total. This is also indirectly confirmed in SDMA section saying "An internal peripheral bus connected to the Shared Peripherals Bus Interface (SPBA) that enables access to up to 14 shared peripherals."
I need this information to properly enable/disable SPBA clock for peripherals connected via SPBA.
You may look at Figure 1-2 (Simplified Block Diagram) of the i.MX6 SL Reference Manual.
For more details please refer to Table 2-5 (SDMA peripheral memory map)
Have a great day, Yuri
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Thank you for reference to memory map. It's actually contains another 2 tables: Table 2-2 (AIPS1 MM) and Table 2-3 (AIPS2 MM). It's differs between iMX6 SL and Q. The only way to access Shared Peripherals are via AIPS1 for SL variant. Table 2-2 says it's accessed via SPBA. But iMX6Q has both AIPS1 and AIPS2 with Shared Peripherals. AIPS1 is similar to SL. AIPS2 looks like direct access for the rest of Shared peripherals.
