What's MMDC PHY ODT control register(MMDC_MPODTCTRL)?

kwangbogham · ‎07-01-2015

Dear everyone,

I'm preparing something to do the DDR stress test for i.MX6 solo lite with DDR3.

The attached document is provided from Freescale field engineer and is to make Aid file before test starts out.

As you know in the attached file, there are some "MMDC Control Parameter" to set the ODT.

Here are some question.

1. What's an affection of four parameter (ODT3_IN_RES, ODT2_IN_RES, ODT1_IN_RES and ODT0_INT_RES) in MPODTCTRL register?

which one? just only DQ(data line) or not?

Maybe i think that four parmeter make an affection to DQ line.

2. If four parameter is for only DQ(data line),

What we are interfacing with i.mx6 solo lite is DDR3 memory.

it's 16bit data bus.

I don't know that i must control and set which parameter of above four parameter?

plz, let me know that i must to control which one.

3. Why is there four parameter ?

Plz, let me explain in more detailed what's the purpose each other?

4. In the attached file, "control bit setting' is default 1(decimal). it means that Rtt resistor is 120 ohm.

Is it recommandation value or not?

Best & Regards,

Kwangbog HAM

igorpadykov · ‎07-01-2015

Hi kwangbog

1. yes this is data lines, per byte control

2.3. recommended to run ibis modelling (check IMX6DQ6SDLHDG

Chapter 9 Understanding the IBIS Model) to choose best option

4. one can start with script for i.MX6SL EVK,

then change it for custom board (if necessary), based on DDR test results

Best regards

igor

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