Using cache and SDMA

[Markon]

Hi, everybody. I have system based on iMX6, FreeRTOS. I need copy table from one point of memory to another. I use for this task SDMA. Memory attribute is write-back cacheable. Before starting copy by SDMA, I clean data cache by MVA to point of coherency and I use DSB to stop CPU to be sure, data are in memory. Then I start copy by SDMA.

My problem is, that one per thousands times, SDMA copies old data.

I don't know, which question is the most suitable.

Why CPU doesn't wait for data would place in memory?

Should be any signal from memory to CPU to inform data are in memory?

[Yuri]

Hello,

  You may look at erratum ERR004325 [ARM/MP: 764369—Data or unified cache

line maintenance operation by MVA may not succeed on an Inner Shareable memory region]

and try its workaround.

https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf

Have a great day,

Yuri

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[Markon]

Thank you for your advice. I checked it and it isn't suitable to my problem.
I work on this problem and now I'm sure:
- that data are copied to memory and CPU doesn't stall when I use DSB or
- addresses data in memory are different than address for starting SDMA and in spite of DSB, CPU change the order of executing software.

[Yuri · Accepted solution]

Hello,

  The i.MX6 does not provide hardware coherency mechanism for external regarding CPUs (say, DMA)
transactions. To avoid coherency issues it is recommended to use special zones, that are marked as non-
cacheable.

Regards,

Yuri.

[Markon]

Thank you for your answer. This answer is the most suitable for my problems.

Regards,

Marcin