Using RGMII compatible PHY with i.MX6 (u-boot)

[tomasznowak]

On our board we would like to use a RGMII-PHY together with i.MX6DL.

The MAC and PHY are connected similiar to the SABRE reference board, the main difference is that the ENET_REFCLK pin which is not connected at all.

I assume this is OK, according to the "Hardware Development Guide" (chapter 12.3 Generating the reference clock) "the pin labeled “ENET_REF_CLK” in Figure 12-2 is only required by the full MII interface.

It is not used by the RMII interface."

Based on this I made further customization (compared to the "sabre-sd" board configuration):

* setting bit ENET_CLK_SEL in GPR1

* configuring (internal) ENET PLL to generate ethernet reference clock (125Mhz),

Unfortunatelly u-boot fails to ping another host, I'm getting "TX timeout packet" error. I suppose this could be caused by missing reference clock.

I checked already that management interface to the PHY works but the RGMII_TXC line doesn't show any activity (during ping command).

Did anybody encounter similiar problems?

Is it possible to route ENET PLL to ENET_REF_CLK (internally - using IOMUX) or does it have to be routed externally (i.e. from GPIO16 or PHY generating 125Mhz)?

Thank you for any feedback

[Yuri · Accepted solution]

   Chapter 11 (Using the RMII Interface) of the Hardware Development Guide for

i.MX6 describes RMII options :  "There are two possible pins that can either

source or sink the reference clock: GPIO_16 and RGMII_TX_CTL."

  GPIO_16 is intended for RMII reference clock; ENET_REF_CLK is intended for

RGMII reference clock. Next, ENET_REF_CLK is input clock, that is - an external

source should be applied - this has been validated.

Note that the ENET_REF_CLK input on MX6 is fed via NVCC_ENET supply rail.

The internal source has to be routed externally from GPIO_16 to ENET_REF_CLK.

So even if customers use the internal clock they would still need to bring

it back in on the ENET_REF_CLK pin.