Hi Ko-hey
1. SION bit does not affect CSI0_DATA_EN_POL.
>2. Do we need to set something CSI0_DATA_EN_POL field ?
No.
> If the DATA_EN is LOW, regardless of the behavior of CSIx_HSYNC, CSIx_VSYNC and CSIx_PIXCLK, data isn't latched.
>Is it correct ?
Yes.
> Data is latched only when the period of DATA_EN is HIGH.
>Is it correct ?
Yes.
~igor
Hi Ko-hey
yes this is correct : it is active high and one can
turn on internal pull-up of CSIx_DATA_EN pad.
When low, the CSI can't latch a data.
Best regards
igor
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Hi Igor
Thank you for your reply.
Let me confirm more detail.
Is it correct ?
When we use DATA_EN with CSIx_HSYNC, CSIx_VSYNC and CSIx_PIXCLK at the same time, my understanding is as follow.
Is it correct ?
Is it correct ?
Ko-hey
Hi Ko-hey
1. SION bit does not affect CSI0_DATA_EN_POL.
>2. Do we need to set something CSI0_DATA_EN_POL field ?
No.
> If the DATA_EN is LOW, regardless of the behavior of CSIx_HSYNC, CSIx_VSYNC and CSIx_PIXCLK, data isn't latched.
>Is it correct ?
Yes.
> Data is latched only when the period of DATA_EN is HIGH.
>Is it correct ?
Yes.
~igor