UART output garbled

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911件の閲覧回数
caibai
Contributor III

hi,

    i run FreeRTOS on cortex-M4 and linux on cortex-A9,when i run demo app <FreeRTOS_BSP_1.0.0_iMX6SX/examples/imx6sx_sdb_m4/demo_apps/low_power_imx6sx/periodic_wfi_qspi> and cortex-M4 uart garbled after linux startup,it seems that uart clock is change,what can i do?

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682件の閲覧回数
Carlos_Musich
NXP Employee
NXP Employee

Hi cai bai,

Sometimes there are problems in clock sync when A9 starts. Run your system and stop the bootloader, then apply the following commands and run your application.

env default -a

setenv fdt_file imx6sx-sdb-m4.dtb

setenv bootcmd "run m4boot;${bootcmd}"

setenv mmcargs "${mmcargs} uart_from_osc"

saveenv

Please let me know if it works.


Regards,
Carlos

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683件の閲覧回数
Carlos_Musich
NXP Employee
NXP Employee

Hi cai bai,

Sometimes there are problems in clock sync when A9 starts. Run your system and stop the bootloader, then apply the following commands and run your application.

env default -a

setenv fdt_file imx6sx-sdb-m4.dtb

setenv bootcmd "run m4boot;${bootcmd}"

setenv mmcargs "${mmcargs} uart_from_osc"

saveenv

Please let me know if it works.


Regards,
Carlos

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

682件の閲覧回数
caibai
Contributor III

it work now ,thank you very much

682件の閲覧回数
caibai
Contributor III

i find that uart root clock will change from osc to PLL3 ,so when i get this change on cortext-M4, then reconfigure uart like

DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR,80000000,115200);

but it also output garbled.

when are the clock init in linux

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