TXC_DLY bit in iMX8 Nano ENET_ECR register broken?

[frank_vanhooft]

We're using an iMX8 Nano, using it's RGMII interface to connect to a gigabit ethernet switch. When I scope the transmit clock & data lines I see they're almost exactly aligned. Which is bad - the switch needs them to be approximately 1/4 period apart.

So I set the TXC_DLY bit in the ENET_ECR register. And the transmit clock disappears! Data is still present, but no clock.

I think I'm going crazy, but when I clear the TXC_DLY bit, the transmit clock reappears. It's fully repeatable.

I don't see anything about this in the errata. 

Any idea what's going on? Is this a known issue? Is there a special procedure required for setting this bit to make it work?

Thanks.

[igorpadykov]

Hi frank_vanhooft

unfortunately this bit (TXC_DLY) is not supported on i.MX8M familiy, supported only for i.MX8QXP/QM.

Best regards
igor

[frank_vanhooft]

This is incredibly frustrating. So you're saying that this is a known hardware problem, but it's not mentioned in the reference manual (which according to the NXP website was updated 15 Jan 2021, although the document itself says Nov 2020), and, it's also not mentioned in the errata. So how the .... are we supposed to know this?  We wasted a whole bunch of time working on a weekend trying to hunt this bug down. 

What about the related bit - RXC_DLY - does that work, or is that broken on the Nano as well?

What else in the Nano is a known issue but undocumented? Is there anything?

Thanks a lot,

Frank.