Spread Spectrum Clocking(SSC) of i.MX6Q PCIe PHY

[torus1000]

Hi,

I have a couple of questions as following.

• Does L4.1.15 BSP for MCIMX6Q-SDP support SSC?
• Is SSC enabled after reset?
• Is there any documents how to set following registers?
     PCIE_PHY_SS_PHASE 　　　　　(5h)
     PCIE_PHY_SS_FREQ 　　　　　(6h)
     PCIE_PHY_SSC_OVRD_IN　　（13h）
     PCIE_PHY_SSC_ASIC_IN　　　（1Ah）

Can someone help me?

[andreagreco]

RefManual told about:

IOMUXC_GPR1 Bit 16 REF_SSP_EN

PCIe_PHY - Reference Clock Enable for SS function. Function: Enables the reference clock to the
prescaler. The phy_ref_ssp_en signal must remain deasserted until the reference clock is running at the
appropriate frequency, at which point phy_ref_ssp_en can be asserted. For lower power states,
phy_ref_ssp_en can also be deasserted.

0 PCIe PHY reference clock is disabled

1 PCIe PHY reference clock is enabled

My cospiration about this:

Seems like that this bit simple enable Ref_CLK to PCIe Phy Prescaler.

In-fact in Linux driver define name is IMX6Q_GPR1_PCIE_REF_CLK_EN.

So as explain in manual Linux driver turn on PCIe Phy then enable ref_clk.

file: drivers/pci/dwc/pci-imx6.c

static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)

{

[...]

        switch (imx6_pcie->variant) {

        case IMX6Q:

                /* power up core phy and enable ref clock */

                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

                                 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);

                /*

                 * the async reset input need ref clock to sync internally,

                 * when the ref clock comes after reset, internal synced

                 * reset time is too short, cannot meet the requirement.

                 * add one ~10us delay here.

                 */

                udelay(10);

                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

                                 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

                break;

[...]

}

static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)

{

[...]

        ret = imx6_pcie_enable_ref_clk(imx6_pcie);

        if (ret) {

                dev_err(dev, "unable to enable pcie ref clock\n");

                goto err_ref_clk;

        }

        /* allow the clocks to stabilize */

        usleep_range(200, 500);

[...]

}

After usleep_range i think is time to configure spread spectrum params whi PCIe_phy_register in the question

PCIE_PHY_SS_PHASE 　     (05h) Seems not really related with SpeadSpectrum
PCIE_PHY_SS_FREQ 　　　(06h) Default value i think could just work, or a minimal effect suld just be osservabble with Scope
PCIE_PHY_SSC_OVRD_IN    (13h) I think this i most important register for enable SS function,

but bit SSC_OVRD_IN_EN is really mysterious, i try set it but without result.

PCIE_PHY_SSC_ASIC_IN      (1Ah) This is in only read and read it return 0.

I do it with appropiate function:

#define PCIE_PHY_SS_FREQ 0x06

#define PCIE_PHY_SSC_ASIC_IN 0x1A

#define PCIE_PHY_SSC_OVRD_IN 0x13

#define PCIE_PHY_SSC_OVRD_IN_SSC_OVRD_IN_EN     (1 << 11)

#define PCIE_PHY_SSC_OVRD_IN_SSC_EN             (1 << 10)

#define PCIE_PHY_SSC_OVRD_IN_SSC_RANGE(x)       ( (x & 0x3) << 8)

#define PCIE_PHY_SSC_OVRD_IN_SSC_REF_CLK_SEL(x) (x & 0xFF)

static inline void imx6_pcie_phy_ss_config(struct imx6_pcie *imx6_pcie)

{

        int ssc_ovrd_in, tmp;

        int ret;

        ret = pcie_phy_read(imx6_pcie, PCIE_PHY_SS_FREQ, &tmp);

        if(ret)

                goto fallied;

        printk("\nPCIE_PHY_SS_FREQ REG:0x%04X\n", tmp);

        ret = pcie_phy_read(imx6_pcie, PCIE_PHY_SSC_OVRD_IN, &ssc_ovrd_in);

        if(ret)

                goto fallied;

        tmp =   PCIE_PHY_SSC_OVRD_IN_SSC_OVRD_IN_EN |

                PCIE_PHY_SSC_OVRD_IN_SSC_EN |

                PCIE_PHY_SSC_OVRD_IN_SSC_RANGE(0x3) |

                PCIE_PHY_SSC_OVRD_IN_SSC_REF_CLK_SEL(0xFF);

        printk("\ntmp:0x%04X\n", tmp);

        printk("\nssc_ovrd_in:0x%04X\n", ssc_ovrd_in);

        ret = pcie_phy_write(imx6_pcie, PCIE_PHY_SSC_OVRD_IN, ssc_ovrd_in | tmp);

        if(ret)

                goto fallied;

        ret = pcie_phy_read(imx6_pcie, PCIE_PHY_SSC_OVRD_IN, &ssc_ovrd_in);

        if(ret)

                goto fallied;

        printk("\nRead ssc_ovrd_in:0x%04X\n", ssc_ovrd_in);

        ret = pcie_phy_read(imx6_pcie, PCIE_PHY_SSC_ASIC_IN, &tmp);

        if(ret)

                goto fallied;

        printk("\nASIC REG:0x%04X\n", tmp);

        return;

fallied:

        printk("Fallied with err:%d\n", ret);

}

At this point i think is time tu assert phy_ref_ssp_en cit in ref manual, but this bit seems not exist.

So, is really possible enable SpreadSpectrum over PCIe ref clock?

Maybe that PCIe_phy shuld be configurate before some reset are cleared, or somethink like that.

For sure in i.MX6DL, do that before ref_clk enable cause reset.

In my case is importat spread  ref_clk because 100Mhz create some subarmonics in GLONAS band (100Mhz*16) 1.60Ghz.

My idea of clock tree
+--------+      +--------------+
|ENET_PLL| ---> | PCIe_phy mpll| 
+--------+      +--------------+
                        |
                        | 100Mhz ref_clk
                        |
                +---------------------+             +----------------+
phy_ref_ssp_en -| PCIe_PHY_ref_clk Gen| ------------|PCIe_PHY_ref_clk| -- Ref_clk_out
                +---------------------+             +----------------+

Can NXP be more clear about this, and told us if is possible enable SS.

[igorpadykov · Accepted solution]

Hi torus1000

>Does L4.1.15 BSP for MCIMX6Q-SDP support SSC?

no

>Is SSC enabled after reset?

no

>Is there any documents how to set following registers?

no

you can get some additional details creating service request:

How to submit a new question for NXP Support 

Best regards
igor
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