SGTL5000 PLL startup/reconfiguration problems

[jonashöppner]

Hello everybody,

we are have a custom board with the i.MX53 and the sgtl5000 codec. The codec MCLK is driven by the mcu's cko2 at 24.576 MHz and generates the I2S frame- and bitclock using the internal PLL.

The OS is linux build the the yocto freescale BSP and the kernel version is 3.0.35.

When I'm playing audiofiles with different samplerates ( 8, 16, 22.05 and 44.1 kHz) with aplay one after another a few time, the codec stops playing:

- No audio output

- sometimes but not always the PLL_LOCKED bit in the SGTL5000_CHIP_ANA_STATUS is not set.

- the frame clock is at a wrong frequency, most of the times about 7kHz

- the I2C communication is still working, though the MUTE bits cannot be set anymore.

Sometimes this happens directly after boot. I haven't found a way to get out of this state except for reboot/powercycle.

As a try I have changed the driver to first switch of the PLL, reconfigure and switch on again. Now it is happening

less often but still. In the manual I only found the PLL startup sequence.

Has anybody seen a similar behaviour, or is there any advise how to handle this state?

Regards, Jonas

[jonashöppner · Accepted solution]

The problem seems to be resolved by adding the correct asound.conf files to the image ( they have been missing in mine).

[art]

This seems to be the possible effect of the SGTL5000 power silicon erratum, please refer to the SGTL5000 Chip Errata document.

Have a great day,
Artur

[jonashöppner]

Thanks, Artur,
but the errata http://cache.freescale.com/files/analog/doc/errata/SGTL5000ER.pdf only contains an startup problem of the VDDD.

In the situation described in the errata, the I2C lines are held low, breakin all I2C communication on the bus. In my situation I2C is still functional.

Also the codec has already played audio before and stops after reconfiguration.

Any other Ideas?