Hi,
In the iMX8QM, I am trying to do a reset catch.
For this I am setting the EDECR.RCE to 1 and necessary steps to do the warm reset from software( RMR_ELn.RR=1).
The target is gettting reset, but it is not stopping at reset vector.
Do i need to do anything else to make this happen?
Regards,
ranjith
Hi Igor,
I would like to reset the first A53 core and halt it at the reset vector.
For this I am using the RMR_EL2.RR bit.and for catching at the reset, I am setting EDECR.RCE bit.
The core is getting reset and it starts running. So when i check thestatus of EDECR, it has been cleared.
What kind of reset it do when RR is set? A warm reset or cold reset? If it is a warm reset the register should not clear isnt it?
Is ARMv8-A DoPD is implemented in iMX8QM? If it is not, EDECR comes in Debug power domain as per ARM v8-A specification.
So it should not clear even if a cold reset is done. What could be the reason for the register is getting reset?
Regards,
Ranjith
Hi Ranjith
in i.MX8 series it is not possible to manipulate A53 core directly, it is done through SCU
System Controller Unit (SCU) Introduction for i.MX 8QXP MEK - i.MXDev Blog
Best regards
igor
HI,
Thanks Igor for the support.
So, is ther any way to halt the the A53 cores at reset vector in iMX8QM?
regards.
Ranjith
Hi Ranjith
one can look at documentation included in SCFW Porting Kit
for available reset options.
Best regards
igor
Hi Ranjith
for reset examples one can look at:
imx8.c\platform\user - m4ctrl - M4 Control Tool for i.MX platforms
Please be aware of partition reset. This will reset only a part of the SoC. It does not rerun the ROM
so code will not be reloaded. By default ATF does a partition reset, not a board reset.
https://community.nxp.com/docs/DOC-341481
Best regards
igor
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