Hi all
I want to receive data that are in BT.1120 DDR mode with i.MX6DL.
However, I have not been successful.
Does the i.MX6DL get the first SAV data with positive edge ?
I checked the following documents but couldn't find a description about it.
4.11.10.2.1 BT.656 and BT.1120 Video Mode
http://cache.nxp.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf
38.4.3.6.4 BT.1120 mode
http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf
I need to understand the timing spec detail because those data are from FPGA.
Ko-hey
解決済! 解決策の投稿を見る。
From reference manual, you can send the first data 0xFF at positive edge of pixel clock.
From reference manual, you can send the first data 0xFF at positive edge of pixel clock.
Hi Qiang Li
What does the blue box mean in the Figure 37-21 ?
I can't understand the meaning of blue box.
Ko-hey
I think it shows when will CSI capture the data. It hasn't cover all pixels, just the example for some pixels.
Do you mean the blue box shows the timing that CSI latch data ?
Ko-hey
Yes
To summarize this topic, the correct figure is as below.
Is it correct ?
Ko-hey
No, the data change should happen at clock edge, not sample the data at clock edge.
So the following figure is correct ?
Ko-hey
Yes
Ok, Thanks.
Ko-hey