Receiving data with positive edge in BT.1120 DDR mode

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Receiving data with positive edge in BT.1120 DDR mode

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ko-hey
Senior Contributor II

Hi all

I want to receive data that are in BT.1120 DDR mode with i.MX6DL.

However, I have not been successful.

Does the i.MX6DL get the first SAV data with positive edge ?

I checked the following documents but couldn't find a description about it.

4.11.10.2.1 BT.656 and BT.1120 Video Mode

http://cache.nxp.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf

38.4.3.6.4 BT.1120 mode

http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

I need to understand the timing spec detail because those data are from FPGA.

Ko-hey

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qiang_li-mpu_se
NXP Employee
NXP Employee

pastedImage_0.png

From reference manual, you can send the first data 0xFF at positive edge of pixel clock.

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qiang_li-mpu_se
NXP Employee
NXP Employee

pastedImage_0.png

From reference manual, you can send the first data 0xFF at positive edge of pixel clock.

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ko-hey
Senior Contributor II

Hi Qiang Li

What does the blue box mean in the Figure 37-21 ?

I can't understand the meaning of blue box.

Ko-hey

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qiang_li-mpu_se
NXP Employee
NXP Employee

I think it shows when will CSI capture the data. It hasn't cover all pixels, just the example for some pixels.

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ko-hey
Senior Contributor II

Do you mean the blue box shows the timing that CSI latch data ?

Ko-hey

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qiang_li-mpu_se
NXP Employee
NXP Employee

Yes

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ko-hey
Senior Contributor II

To summarize this topic, the correct figure is as below.

Is it correct ?

image001.png

Ko-hey

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qiang_li-mpu_se
NXP Employee
NXP Employee

No, the data change should happen at clock edge, not sample the data at clock edge.

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ko-hey
Senior Contributor II

So the following figure is correct ?

image001.png

Ko-hey

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qiang_li-mpu_se
NXP Employee
NXP Employee

Yes

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ko-hey
Senior Contributor II

Ok, Thanks.

Ko-hey

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