My code actually is the following:
arch/arm/include/include/asm/arch-mx6/mx6sx_pins.h has the following changes:
MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x03D8, 0x0090, 1 | IOMUX_CONFIG_SION, 0x0760, 1, 0),
MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x03E8, 0x00A0, 1 | IOMUX_CONFIG_SION, 0x076C, 1, 0),
board specific code looks:
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define GPIO_FEC1_PHY_RESET IMX_GPIO_NR(2, 7)
static iomux_v3_cfg_t const fec1_pads[] = {
MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* ENET PHY Reset */
MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
....
static int voneus_enable_fec_anatop_clock(enum enet_freq freq)
{
extern struct mxc_ccm_reg *imx_ccm;
u32 reg = 0;
s32 timeout = 100000;
if (freq < ENET_25MHz || freq > ENET_125MHz)
return -EINVAL;
reg = readl(&imx_ccm->analog_pll_enet);
reg &= ~(BM_ANADIG_PLL_ENET_DIV_SELECT|BM_ANADIG_PLL_ENET2_DIV_SELECT);
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq) | BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
writel(reg, &imx_ccm->analog_pll_enet);
while (timeout--) {
if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
break;
}
if (timeout < 0) {
printf("FEC MXC: %s:timeout\n", __func__);
return -ETIMEDOUT;
}
}
/* Enable FEC clock */
reg |= BM_ANADIG_PLL_ENET_ENABLE|BM_ANADIG_PLL_ENET2_ENABLE;
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
#ifdef CONFIG_FEC_MXC_25M_REF_CLK
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
#endif
writel(reg, &imx_ccm->analog_pll_enet);
return 0;
}
static int probe_lan8720(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
{
uint32_t base_mii;
struct mii_dev *bus = NULL;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
#endif
int ret;
base_mii = addr;
printf("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
bus = fec_get_miibus(base_mii, dev_id);
if (!bus)
return -ENOMEM;
#ifdef CONFIG_PHYLIB
phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RMII);
if (!phydev) {
free(bus);
return -ENOMEM;
}
ret = fec_probe(bd, dev_id, addr, bus, phydev);
#else
ret = fec_probe(bd, dev_id, addr, bus, phy_id);
#endif
if (ret) {
#ifdef CONFIG_PHYLIB
free(phydev);
#endif
free(bus);
}
return ret;
}
int board_eth_init(bd_t *bis)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
int ret;
int reg;
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
gpio_direction_output(GPIO_FEC1_PHY_RESET, 0);
reg = readl(&iomuxc_gpr_regs->gpr[1]);
/* reset ENET1/2_TX_CLK_DIR gpr1[14:13] to set reference clock driven by ref_enetpll0/1
* Clock is output to pins via IOMUX ENET_REF_CLK1/2
*/
reg &= ~(IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK|IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
/* set ENET1/2_TX_CLK_DIR gpr1[18:17] to enable output driver when ENET1/2_TX_CLK when in ALT1 */
reg |= IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK|IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK;
writel(reg, &iomuxc_gpr_regs->gpr[1]);
ret = voneus_enable_fec_anatop_clock(ENET_50MHz);
enable_enet_clock();
mdelay(30);
gpio_set_value(GPIO_FEC1_PHY_RESET, 1);
mdelay(100);
ret = probe_lan8720(bis, CONFIG_FEC_ENET_DEV, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
if (ret)
printf("FEC MXC: %s:failed (%0x)\n", __func__, ret);
return ret;
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
