Questions about iMX6 parallel display pixel clock limit

[xjgan]

     We have a customized imx6q(d) board. To the LCD interface, we found that the larger pixel clock is, more disorder the display will be. This will become obvious when pixel clock goes beyond 40Mhz.

     For an example,  we try to attach a LCD to the parallel RGB port. The LCD parameters are 18bpp(rgb666), 720x1280, 60hz, pixel clock is about 57Mhz. According to the data sheet of the LCD, we set proper timing in the kernel source 'mxc_lcdif.c'. But the display seems to be messed enough.

     We captured the signal of the DI0_DISP_CLK (pixel clock of RGB signals), the waveform seems mess too.

     And then, we set the refresh frequency from 60hz to 30hz (in order to downgrade pixel clock without cropping image). Except the refresh frequency, none of the timing items are changed. Then, the display looks good.

      Again, we captured the signal of the DI0_DISP_CLK (pixel clock of RGB signals), the waveform looks clean.

     We removed LCD from the port, and tried several RGB timing settings with different pixel clocks. Finally, we conclude the result mentioned at the beginning of article. We are using BSP package from 'L3.0.35_1.1.0_121218_source', with patch 03&04 applied. The waveforms of pixel clock are captured from the position most nearby the CPU.

[Yuri]

  Perhaps the problem relates to the fact, that output IPU pixel clock for LCD may have high jitter.

That's the expected behavior when the clock divider is set to a value that is not an integer.

Please look at IPU hardware parameters Tdicp and Tdpcp in the Datasheet(s).

When the divider is set to a non-integer value, the average frequency of the display clock will be
correct - but the clock will jitter. For applications that are sensitive to jitter, it may be recommended
to apply a clock ratio combination that allowed the clock divider to be set to an integer value.