Question, i.MX6DQ DDR_SEL setting

[Aemj]

Hi All,

I would like to ask about IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register of i.MX6DQ.

Should one set 11b into the DDR_SEL field in the case of using 1.8V/2.5V PHY?

Or, can DDR_SEL be default value(10b) regardless of the IO voltage of PHY?

Please give your answer to the above, and the explanation about this DDR_SEL setting as well.

BR,

Miyamoto

[Yuri · Accepted solution]

DDR_SEL should be set as 11 for RGMII interface (for signals ranging from 1.3V to 2.5V).