Pin muxing on NXP i.MX8M Plus EVK

[Jonarie]

Hi,

I'm trying to Mux ECSPI2_SCLK to GPIO5_IO10 (output) and ECSPI2_SS0 to GPIO5_IO13 (input).
But something (at least for me) unexplainable happens, when I configure GPIO5_IO13 as Input with weak Pull Down [ pad = ( pad & (~0x1f6) ) | (1 << 8); ] , the pin has like a capacity, similar to a connected capacitor. If I connect it to 3.3V via a Jumper wire, it holds the voltage until I short it with GND.

This capacitive bahaviour is so strong, that most of the time its not possible to pull the pin down with another output pin.
That results in a "between state" of this pin, where it is at aprox. 1.8 V and still reads as high (see attachment).

My board rund QNX 7.1 btw.

I hope someone can help me with my Issue.

Below is my initialisation code:

out32(iomuxc + IMX_IOMUXC_SW_MUX_CTL_PADx(IMX_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK), IMX_MUX_CTL_MUX_MODE_ALT5 | (1 << 4)); /* SCLK, as GPIO5_IO10*/
out32(iomuxc + IMX_IOMUXC_SW_MUX_CTL_PADx(IMX_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0), IMX_MUX_CTL_MUX_MODE_ALT5 | (1 << 4)); /* SS0, as GPIO5_IO13*/

gdir |= trigger_pin; // GPIO5_IO10
gdir &= ~irq_pin; // GPIO5_IO13

pad_ctl = (pdir10 & (~0x1f6)) | (3 << 1); // GPIO5_IO10
pad_ctl = (pdir13 & (~0x1f6)) | (1 << 8); // GPIO5_IO13

In the bsp init_pads.c is the following configured for ECSPI2:

/**
* ECSPI mux and electrical properties.
*
* @return Execution status.
*/
static int imx_init_ecspi_pads(void)
{
/* ECSPI 2 */
/* CLK */
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_SW_MUX_CTL_PADx(IMX_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK), IMX_MUX_CTL_MUX_MODE_ALT0);
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_INPUTx(IMX_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT), 1);
/* MOSI */
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_SW_MUX_CTL_PADx(IMX_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI), IMX_MUX_CTL_MUX_MODE_ALT0);
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_INPUTx(IMX_IOMUXC_ECSPI2_MOSI_SELECT_INPUT), 1);
/* MISO */
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_SW_MUX_CTL_PADx(IMX_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO), IMX_MUX_CTL_MUX_MODE_ALT0);
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_INPUTx(IMX_IOMUXC_ECSPI2_MISO_SELECT_INPUT), 1);
/* CS */
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_SW_MUX_CTL_PADx(IMX_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0), IMX_MUX_CTL_MUX_MODE_ALT0);
out32(IMX_IOMUXC_BASE + IMX_IOMUXC_INPUTx(IMX_IOMUXC_ECSPI2_SS_B_SELECT_INPUT_0), 1);

return 0;
}

[Jonarie]

Meanwhile I've got the Impression, that my ambitions to configure the pad_ctl registers are not taking any effect, as if I configure the weak pullup or down, there is definetly no pullup/down on that pin.

Below you can see how I configure the pad_ctl registers:

uintptr_t iomuxc = mmap_device_io(IMX_IOMUXC_SIZE, IMX_IOMUXC_BASE);
uintptr_t pad13_ctl = iomuxc + IMX_IOMUXC_SW_PAD_CTL_PADx(IMX_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0);
uint32_t pad13_cfg = in32(pad13_ctl);
pdir13 = (pad13_cfg & (~0x1f6)) | (1 << | (1 << 6);
out32(pad13_ctl, pad13_cfg);

As a weak pullup as specifyed in Processors Reference Manual IMX8MPRM.pdf on page 1814.

[Jonarie]

EDIT:
pdir13 = (pad13_cfg & (~0x1f6)) | (1 << | (1 << 6);

[Jonarie]

EDIT:

In the meantime I recompiled the BSP with ECSPI2 disabled, but still the same behaviour.

[Alejandro_Salas]

Hello @Jonarie 

I hope you are doing well.

Are you still having the issue?

Also, could you please confirm that behavior is just for that pad? or other pads have the same behavior?

Best regards,

Salas.

[Jonarie]

Hi @Alejandro_Salas,
thanks for your message!
Yes, I'm still having that issue, and the issue also occurs on other pads.