PCIe Clocks

[b_neperud]

We are trying to get PCIe working with Linux on a custom board with an i.MX6Q and an external PCI clock generator, using the linux-imx_4.19.35 Yocto warrior kernel.

I've seen Setting the iMX6 PCIe Clocks and other posts saying the 100 MHz SATA clock must be enabled to access PCIe registers, but my experience seems to indicate the opposite:

• With CCM_ANALOG_PLL_ENET bit 20 (ENABLE_100M) set to enable the SATA clock, the kernel hangs when it first tries to access PCI registers (specifically, when it goes to read MPLL_OVRD_IN_LO in setting up for the external clock).
• With CCM_ANALOG_PLL_ENET bit 19 (ENABLE_125M) set instead (bit 20 is 0), the kernel is able to access PCI registers, we end up with the "phy link never came up" message instead.

In other words, what we see is that PCI register access requires the 125M PCIE clock be enabled, but the community says PCI register access requires the 100M SATA clock be enabled. Any ideas to explain the difference?

[weidong_sun · Accepted solution]

Hello Bryan,

 Here is the patch for using external PCIe reference clock,  probably it is not the same linux bsp as yours, but you can add it to your version of linux bsp manually.

Have a nice day!

B.R,

weidong

[b_neperud]

Hi Weidong,

The changes in this patch are actually already in the bsp we're using.

I guess that sort of answers my question though. It looks like the changes for the 6QP sabresd board to use an external PCI clock are using the IMX6QDL_CLK_PCIE_REF_125M clock rather than the IMX6QDL_CLK_SATA_REF_100M clock, which matches what has been working for us. I still don't get why I've seen multiple posts here say the 100M clock is needed, maybe that information is inaccurate or maybe I've been misunderstanding something. This has all been confusing to sort through.

Thank you,

Bryan