Output BT656 from iMX6Q to ADV7391

[sebastiancabot]

Hello

I am trying to output BT656 to the ADV7391 but the output is distorted (Please see attached video)

(The pattern I am writing to the frame buffer is:

WHITE:  90 Columns

RED:    180 Columns

Green:  180 Columns

Blue:     180 Columns

Black:    90 Columns

)

We have our own board based on the Hummingboard2 from Solidrun.

I am using the latest patches for 3.14.52 from: Patch to Support BT656 and BT1120 Output For i.MX6 BSP 

The ADV7391 is connected to IPU1 DISP1 using DATA lines 0 to 7.

HDMI is connected to IPU1 DISP0

Here is the fb definition:

    mxcfb2: fb@1 {
        compatible = "fsl,mxc_sdc_fb";
        disp_dev = "adv739x";
        interface_pix_fmt = "BT656";
        mode_str = "BT656-NTSC";
        default_bpp = <16>;
        int_clk = <0>;
        late_init = <0>;
        status = "okay";
    };

    &i2c3 {
    clock-frequency = <100000>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_hummingboard2_i2c3>;
    status = "okay";
    adv7391: adv7391@2b {
        compatible = "adv,mxc_adv739x";
        reg = <0x2b>;
        pinctrl-names = "enable", "default";
        pinctrl-0 = <&pinctrl_i2c3_adv739x_on>;
        pinctrl-1 = <&pinctrl_i2c3_adv739x_off>;
#define GP_ADV7391_RESET <&gpio3 10 GPIO_ACTIVE_LOW>
        rst-gpios = GP_ADV7391_RESET;
        ipu_id = <0>;
        disp_id = <1>;
    };
};

Here is the pinmux definition:

pinctrl_i2c3_adv739x_on: i2c3-adv7931x-grpon {
            fsl,pins = <
                MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x10 /* CLOCK */
                MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00  0x10
                MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01  0x10
                MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02  0x10
                MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03  0x10
                MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04  0x10
                MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05  0x10
                MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06  0x10
                MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07  0x10
                MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x10 /* HSYNC */
                MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x10 /* VSYNC */
                MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 /* RST */
            >;
        };

Please note that although HSYNC and VSYNC are defined they are not used since BT656 Mode is selected for the device:

Here is the device configuration for NTSC:

static void adv739x_set_ntsc(struct adv739x_data *adv739x)
{
    struct i2c_client *client = adv739x->client;
    // Reg 0x01: SD input
    adv739x_write(client, 0x01, 0x00);
    //NTSC
    // Reg 0x80: SD, NTSC
    adv739x_write(client, 0x80, 0x10);
    // Reg 0x82: SD, CVBS
    adv739x_write(client, 0x82, 0xCB);
    // Reg 0x8A: Timing mode slave use EAV/SAV
    adv739x_write(client, 0x8A, 0x08);
}

And here is the video mode definition:

static struct fb_videomode adv739x_modedb[] = {
    {
     /* NTSC Interlaced output */
     "BT656-NTSC", 60, 720, 480, 37037,
     19, 3,
     20, 3,
     276, 1,
     FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
     FB_VMODE_INTERLACED,
     FB_MODE_IS_DETAILED,},
    {
     /* PAL Interlaced output */
     "BT656-PAL", 50, 720, 576, 37037,
     22, 2,
     23, 2,
     288, 1,
     FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
     FB_VMODE_INTERLACED,
     FB_MODE_IS_DETAILED,},
};

I have changed the BT656_IF_DI_MSB in ipu_disp.c to 7

I have changed the clock definition in clk-imx6q.c to:

imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);  /* For CVBS 27MHz clock */

Looking at dmesg I can see that the clocks are correctly configured:

[   28.061693] imx-ipuv3 2400000.ipu: pixel clk = 27000000
[   28.062233] imx-ipuv3 2400000.ipu: bt656 di clk:108000000
[   28.062260] imx-ipuv3 2400000.ipu: round pixel clk:27000000
[   28.067443] imx-ipuv3 2400000.ipu: div:4

Any help will be appreciated.

Thank you

Sebastian

[sebastiancabot · Accepted solution]

The solution for this problem was to move the HDMI to IPU1.

[qiang_li-mpu_se]

How about your kernel log? Is there any error?

And did you measure the clock pin frequency?

Maybe you can adjust the IOMUX, such as the "0x10":

MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00  0x10

[sebastiancabot]

Hello Qiang Li

There are no errors in the kernel log.

We measured the clock frequency using a scope and it is 27MHz.

Also as mentioned I printed the clock frquencies from ipu_init_sync_panel and the printout suggests the clock is correctly configured to 27MHz

Also the ADV7391 doesn't work if the clock is incorrect and I can use it to output the device's internal BARS pattern correctly so the clock must be correct.

I don't understand your suggestion for the iomux. right now the pins are configured with 0x10.

What would you suggest I use instead?

Thank you very much

Sebastian

[sebastiancabot]

Hello Igor

Thank you for your answer.

I haven't checked this on the reference board.

I don't have access to such a board and even if I did I need to make it work on our board.

Any ideas as to what I can check?

Thank you

Sebastian

[igorpadykov]

Hi Sebastian

had you tried these patches on nxp reference boards with official bsp releases on

i.MX 6 / i.MX 7 Series Software and Development Tool|NXP 

third party boards (like hummingboard) and bsps are supported by its vendors and

one can post it on meta-fsl-arm mailing list
https://lists.yoctoproject.org/listinfo/meta-freescale

Best regards
igor
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