Hello all, im using a Nitrogen6X-SOM along with the host board. Im trying to reconfigure the pinmuxing on it to enable spi out via this post: https://boundarydevices.com/mx6-device-tree-customization/
in the imx6qdl-nitrogen6x.dtsi i have made the following changes: (ECSPI1 was pre-existing and im addint that for reference, my modifications are the ECSPI2 sections)
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1
#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT21__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT22__ECSPI2_MISO 0x100b1
>;
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = GP_ECSPI1_NOR_CS;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mtd@00000000 {
label = "U-Boot";
reg = <0x0 0xC0000>;
};
mtd@000C0000 {
label = "env";
reg = <0xC0000 0x2000>;
};
mtd@000C2000 {
label = "splash";
reg = <0xC2000 0x13e000>;
};
};
};
&ecspi2 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio5 17 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
spidev@00 {
compatible = "spidev";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
The issue im having is that on the 3 lines:
MX6QDL_PAD_DISP0_DAT20__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT21__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT22__ECSPI2_MISO 0x100b1
i get a syntax error on the ECSPI2. If i replace the ECSPI2 with ECSPI1 it compiles. I have checked every included .dts and .h and there are no other references to ECSPI1 that i could find, so there must be something wrong with my syntax in the .dtsi file but i cannot find where.
Solved! Go to Solution.
Please check your hardware design, the pin MX6QDL_PAD_DISP0_DAT20 can't be used as ECSPI2_SCLK, the same case for the other two pins.
The valid function for ECSPI2:
ECSPI2_SCLK: MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK
MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK
ECSPI2_MOSI: MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI
ECSPI2_MISO: MX6QDL_PAD_EIM_OE__ECSPI2_MISO
MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO
Hi Matthew,
Every pin can only be muxed to a limited set of IP. You can't just decide which pin is going to be ECSPI2_CLK, this latter can be used from DISP0_DAT19, CSI0_DAT8 or EIM_CS0.
You need to read the i.MX6QD Reference Manual to learn the possible muxing.
Another tip, look at the kernel pinfunc header, it will give you all the possibilities:
linux-imx6/imx6q-pinfunc.h at boundary-imx_3.14.52_1.1.0_ga · boundarydevices/linux-imx6 · GitHub
Regards,
Gary
I see that i was able to get the muxing correct and i do see the signals go low at boot (which i would expect when it is setting up the dtb)
I do also see an additional interface that i didnt before in linux:
/sys/bus/spi/devices/0.0
/sys/bus/spi/devices/1.0
and
/dev/spidev1.0
Now what i am wondering is if there is any easy way to test/see some sample output through the device to ensure spi is being set up/muxed properly?
Under buildroot i did check the spidev and spi-tools options, but it doesnt actually seem like spi-tools is getting build into linux (not sure why, find . -name *spi*.* does not find any form of spitools).
Hi Matthew,
There might be something wrong with your Buildroot. I just tried it here and building spi-tools provides:
- output/target/usr/bin/spi-config
- output/target/usr/bin/spi-pipe
You can look at the examples here on how to use those tools:
GitHub - cpb-/spi-tools: Simple command line tools to help using Linux spidev devices
Regards,
Gary
Please check your hardware design, the pin MX6QDL_PAD_DISP0_DAT20 can't be used as ECSPI2_SCLK, the same case for the other two pins.
The valid function for ECSPI2:
ECSPI2_SCLK: MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK
MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK
ECSPI2_MOSI: MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI
ECSPI2_MISO: MX6QDL_PAD_EIM_OE__ECSPI2_MISO
MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO