New design based on Sabrelite: DDR3 topology?

[ThomasG1z]

Doing a design that will be closely related to the Sabrelite, but a bit unsecure about the DDR3 solution. I would like all 4 chips to be on the primary side, to ease production, and would think that flyby topology would be best. Also I need the possibility to support the Solo too so the initial plan is to place the lower 2x16 bits at the end of the chain.

1. Does the concept seem fine?

2. If using fly-by are there any DDR3 register changes required compared to the sabrelite? I would really like to be able to boot up a board with the sabrelite uboot. So I have a known working good config. Haven't dove into the details here yet though.

comments...?

[YixingKong]

Thomas

Has your issue resolved by David's reply? If yes, please close the DI, otherwise please keep feeding back your statement here.

Thanks,

Yixing

[ThomasG1z]

Actually we ended up using only a 32-bit bus on our board, for various reasons, and T-point routing. Simulated and tested.

[admin · Accepted solution]

From DavidBabin:

1. Yes, the concept seems fine. Flyby is better method with 4 chips on the primary side. Follow all guidelines in the Hardware Development Guide chap 3 (doc IMX6DQ6SDLHDG) for layout, write leveling, etc. An 8-chip flyby layout is shown; you can eliminate the 4 chips on the bottom. With the Solo option, be sure to minimize stubs.

2. Start with the DDR3 register settings for sabrelite. You may need to tweak drive strength settings to optimize your system.

 
3. Use the design checklist in Hardware Development Guide chap 2.

4. Simulate your layout.