MX6 SSI BCLK and FCLK generation?

[raymondwang]

Nowadays, I read most of discussions in this community on MX6 audio codec driver or BSP porting tutorials.

For my board designed based on sabresd, we adopted new codec Realtek RT5625. And my application is Android JB based.

RT5625  can support most MCLK 12MHz. In this scenario , MX6 works as PCM master and RT5625 as slave.

This is my board init configuration code snippet:

static struct imx_ssi_platform_data mx6_qpad_ssi_pdata = {

  .flags = IMX_SSI_DMA | IMX_SSI_SYN,

};

static struct platform_device mx6_qpad_audio_rt5625_device = {

  .name = "imx-rt5625",

};

static struct mxc_audio_platform_data rt5625_data = {

  .ssi_num = 1,

  .src_port = 2,

  .ext_port = 3,

};

In clock.c ,I changed pll4_audio_main_clk and ssi1 clock.

clk_set_rate(&pll4_audio_main_clk, 180633600);

clk_set_rate(&ssi2_clk, 22579200);

In my imx-rt5625.c

static int imx_hifi_hw_params(struct snd_pcm_substream *substream,

      struct snd_pcm_hw_params *params)

{

  struct snd_soc_pcm_runtime *rtd = substream->private_data;

  struct snd_soc_dai *cpu_dai = rtd->cpu_dai;

  struct snd_soc_dai *codec_dai = rtd->codec_dai;

  unsigned int channels = params_channels(params);

  int ret = 0;

  unsigned int pll_out;

  u32 dai_format;

  dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |

  SND_SOC_DAIFMT_CBS_CFS;

  pll_out = params_rate(params) * 512;

  /* set cpu DAI configuration */

  /* set i.MX active slot mask */

  snd_soc_dai_set_tdm_slot(cpu_dai,

  channels == 1 ? 0xfffffffe : 0xfffffffc,

  channels == 1 ? 0xfffffffe : 0xfffffffc,

  2, 32);

  ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);

  if (ret < 0) return ret;

  /* set the SSI system clock as input (unused) */

  snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN);

  snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 0);

  snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0);

  snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 3);

  /* set codec DAI configuration */

  ret = snd_soc_dai_set_fmt(codec_dai, dai_format);

  if (ret < 0)

  return ret;

  ret =  snd_soc_dai_set_pll(codec_dai, RT5625_PLL1_FROM_MCLK, 0, card_priv.sysclk, pll_out);

  if (ret < 0)

  return ret;

  ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, 0);

  return 0;

}

Now my BCLK is 2.822MHz, FCLK is 44.1kHz. And I can measured audio data in AUD3_TXD, But no sound output in speaker.

I am sure that RT5625 register are configured properly. What's wrong?

Beside that, I don't how to understand relationship for TDM slot ,FCLK,BCLK.  Anyone can explain that in details?

[raymondwang · Accepted solution]

Now it should be fixed, BCLK=2.822MHz because in I2S mode MX6Q always generate 32bit per sample. For stereo ,it is 64bit width.

So 44.1kHz*64 = 2.822MHz.