IMX8MP CSI camera interface RAW10 troubleshooting

[gabrielebrugnon]

Hello.
I'm trying to interface a IMX226C sensor to an IMX8MP SoC.
The device driver is handled by imx8-mipi-csi2-sam.c in the staging directory.
I've patched the driver to handle the MEDIA_BUS_FMT_SRGGB10_1X10 format as RAW10 (MIPI_CSIS_ISPCFG_FMT_RAW10).

The sensor resolution is 3840 x 3020 pixels, it uses 4 lanes at 1500 Mb/s rate. The pixel clock is 72 MHz.

There are some points that are not clear to me:

The DTB has a parameter called "csis-wclk", that in the driver changes the behavior of the bit 0 in the MIPI_CSIS_CLK_CTRL register, but in the reference manual the bits 0-3 are reported as "Reserved".
Could you please clarify to me what is the meaning of this bit?

After some modifications to the driver, I was able to capture images, but with some issues:

When setting PIXEL_MODE to single (MIPI_CSIx_ISP_CONFIGn register), no images are captured because FIFO overflow happens.
When setting PIXEL_MODE to dual or quad, images are captured but are horizontally squeezed on the half (for dual) or on the quarter (for quad) left side, the rest of the pixels in each row is black.

I can't understand the relationship described in the "clock domain" paragraph of the MIPI-CSI Chapter. Could you clarify what are the three clocks described on it?

In the Pixel Alignment figure, it seems that RAW10 data is disposed on a 64 bit bus only in quad pixel mode. The CSC in the ISI module is set to "bypass" by the ISI driver, so how data is transferred to the destination image memory?

Thank you very much in advance for your help.

Regards,
Gabriele.

[dh84]

Hi Gabriele,

I have very similar problems with the mipi csi. (See here https://community.nxp.com/t5/i-MX-Processors/Creating-a-MIPI-CSI-Camera-driver-on-i-MX-8MP-EVK/m-p/1...)

Concerning the wsis-clk, there is a explanation here: 

https://community.nxp.com/t5/i-MX-Processors/Explenation-for-HS-SETTLE-parameter-in-MIPI-CSI-D-PHY-r...

But I don't know if this is also suitable for imx8mp. There is also a tip in the mipi driver:

 * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM

The strange thing is, that the bit is not included in the register description. Maybe someone of NXP support would be so kind to clarify this.

But I'm also a little bit confused about the clock-domain chapter. I think they have the following meanings:

• RxByteCLKSH0 - Byte Clock from DPHY -> MIPI CSI
  • 1500 MBit/s => 187,5 MByte/s => MIPI is DDR => 187,5 MHz / 2 => 93,75 MHz
• I_PCLK - APB Clock used for the AXI register interface of the MIPI Core. The root clock is media_apb_root_clk (200 MHz default)
• I_ACLK - Output Pixel clock that feeds the image output interface. The root clock is media_cam1_pix_root_clk (500 MHz default)

What kind of errors do you see if you enable the debug prints?

echo 2 > /sys/module/imx8_mipi_csi2_sam/parameters/debug

Best regards,

Daniel