IMX8MN EVK GPIO on M7

[k_specka]

Hi, I'm trying to get some LEDs running with the MCUXpresso SDK for the M7.

In the led example tho config looks like:

#define EXAMPLE_LED_GPIO GPIO5
#define EXAMPLE_LED_GPIO_PIN 11U
#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448 //@ fsl_iomuxc.h

IOMUXC_SetPinMux(IOMUXC_SAI3_TXD_GPIO5_IO01, 0U); // @ BOARD_InitPins() pin_mux.c

gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
GPIO_PinInit(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, &led_config);

This seems to use pin 19 of the J1003.
But how can the EXP_IOxx be used? Like pins 15 & 16?
I also would like to use pin18 which has no red/blue naming. How to configure those?

For the linux part on A53 I expect that the device tree needs to be edited to be able to use gpio on both cores?
Is there some information available how the J1003 pins are connectedto the cpu? And which pins share interrupts.

[k_specka]

Thanks for the quick reply.
So all the EXP_IO Pins are used over the I2C. So only accessible on M7 or A53?
Is there some driver and example code available?
At the moment I'm launching the M7 code from u-boot, I expect that the I2C is not occupied from it. Is this correct?

For using gpio on M7/A53 I mean separate ports.
Like the uart ports avaiable via usb for M7 and A53 this seems to be possible.
The possible options of the 'red' pins uart/sai/ecspi of J1003 seem to be clear from fsl_iomuxc.h
Finding schematics is not easy, the design files for the nano evk have the mini docs inside.
It would be nice to have an more detailed doc for the J1003 to show cpu pins which are connected directly.
Maybe the pins for uart share a memory bank and are dedicated to one cpu? (same for sai, ecspi?)
Can you give more details on this?

[AldoG · Accepted solution]

Hello,

I2C3 is indeed in use, it is even defined in the device tree for uboot, so you may need to disable this first.
https://github.com/nxp-imx/uboot-imx/blob/lf_v2022.04/arch/arm/dts/imx8mm-evk.dtsi#L345

I'm not aware of a driver of PCA6416 IC for Cortex-M, but we do have it available for Linux so you may use it as a reference:
https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpio/gpio-pca953x.c

Using different GPIOs on M7/A53 it is indeed possible, just to make a note you may use different GPIO blocks between cores but not the same block, i.e. GPIO1_IO3 (M7) GPIO2_IO4 (A53) is ok, GPIO1_IO3 (M7) GPIO1_IO4 (A53) is not.

For muxing options of the Expansion Connector pads available, you may refer to the i.MX8MMini Base board schematic, in the last page you'll find a table for the whole muxing options of the pads, the first column is the pad muxed usage in the EVK the following columns is the muxing options. Either way I still recommend checking the reference manual for detailed information on the muxing options.

Also, please note that both i.MX8MM and i.MX8MN share schematics for base board since it is the same, even both processors are pin to pin compatible.
https://www.nxp.com/docs/en/application-note/AN12667.pdf
https://www.nxp.com/docs/en/fact-sheet/IMX8MNANOFS.pdf

Hope this helps,
Best regards,
Aldo.

[AldoG]

Hello,

EXP_Ioxx come from the I2C bus expander (PCA6416APW), which is connected to the I2C3 bus, you'll need to disable the I2C3 in the device tree of the Cortex-A so it is available for the Cortex-M, then you'll need to use/create a driver for this IC.

For pin 18 of the Expansion connector as specified in the schematic with an x it is not connected to anything.

Regarding using the same GPIO on both cores this is not possible, you may create an RPMSG code so one of the cores have control over the GPIO and the other just asks about the status of it through RPMSG.

You may check the schematic to see what is connected where, after this you may check reference manual for the available mux options of the pads.

Best regards,
Aldo.