1. The CSI module has the 256 x 64 RxFIFO to store received image pixel data at the speed of the image sensor pixel clock. When the number of remaining empty slots in the RxFIFO reaches the level, specified by the RxFF_LEVEL bits, the interrupt or DMA request is generated and the software or the CSI DMA engine flushes the RxFIFO content to the framebuffer area, located in the main system memory.
2. The CSI module supports so-called double buffer mode, in which it can store two consecutive frames into different frame buffers to simplify further frame processing in software. In case of DMA transfer, the CSI DMA engine switches the base address of the frame buffers after completing the frame transfer. Typical mechanism is that DMA does it automatically immediately after completing a frame transfer. There are two alternate methods of switching the base address: when receiving the next VSYNC edge and when receiving the first data of the next frame to RxFIFO. So, the BASEADDR_SWITCH_EN bit enables these alternate methods, and the BASEADDR_SWITCH_SEL bit selects between them.
Have a great day,
Artur
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