I2S microphone (SPH0645LM4H) Driver Implementation with i.mx6ul

hitesh_kasera · ‎04-17-2019

Hi,

I am working with 1 I2S microphone (SPH0645LM4H) which is connected to i.MX6UL I2s Interface. I want to record audio from this mems. My device tree set up for the same is:

/ {
   sound {
      compatible = "fsl,imx-audio-sph0645",
                           "fsl,imx-mic-sph0645";
      model = "sph0645-audio";
      cpu-dai = <&sai1>;
   };
};

&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;

    /*
     * Reference block.
     *
     * Codec dependent section.
     */
    assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
            <&clks IMX6UL_CLK_SAI1>;
    assigned-clock-rates = <0>, <12288000>;
    assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;

status = "okay";
};

The driver file main code set up like :

u32 channels = 2; //ALWAYS 2 CHANNELS params_channels(params);
u32 rate = params_rate(params); //sampling rate

dev_err(cpu_dai->dev, "sampling rate parms_rate output rate : %d \n" , rate);
u32 bclk = rate * channels * 32; //fixed to sampling rate * 64
dev_err(cpu_dai->dev, "bclk : %d \n" , bclk);

int ret = 0;

   /* set cpu DAI configuration */
   ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
   if (ret) {
       dev_err(cpu_dai->dev, "failed to set dai fmt\n");
       return ret;
   }

   ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 3, 2, 32);
   if (ret) {
       dev_err(cpu_dai->dev, "failed to set dai tdm slot\n");
       return ret;
   }

   ret = snd_soc_dai_set_sysclk(cpu_dai, 0, bclk, SND_SOC_CLOCK_OUT);
   if (ret)
       dev_err(cpu_dai->dev, "failed to set cpu sysclk\n");

Issue is i am not able to get desire bit clock and frame sync clock. for example i run below mentioned command to see signals on oscilloscope.

arecord -c 2 -d 5 -f S32 -r 48000 -v /home/root/test.wav

on oscilloscope i was getting bit clock frequency around 11.086Mhz and Frame sync clock was about 173 Khz. As i am passing 48000 hz sampling rate bclk should be 3.072Mhz but here its not the case. In this case i have not attached the microphone sensor because it could get damaged due to higher frequency. i have also tried to see prints in fsl_sai.c file there i see the mclk_clk[0]= 0Hz and mclk_clk[1]=12.288Mhz.

I tried different sampling rate also such as

arecord -c 2 -d 5 -f S32 -r 16000 -v /home/root/test.wav

In this case i was getting bclk of 3.69Mhz and frame sync of 57.663 Khz which is also not according to what i have requested.

I am not able to get this issue. How its taking 11Mhz?

Thanks & Regards,

Hitesh

weidong_sun · ‎04-17-2019

Hello Hitesh,

See below, please!

1. On SAI1_MCLK

you set assigned-clock-rates = <0>, <12288000>;, which means SAI1_MCLK will output 12.288MHz for your I2S MIC.

So please measure if it's frequency is correct !

2. About bitclk

You set "u32 bclk = rate * channels * 32; //fixed to sampling rate * 64",

--Here rate is sample rate.

--channels : Stereo --2 channels

--32: the bit number of binary encoding.

You can try to change 32 to 16 or 24 or 8, then try record again.

3. Settings of SAI1_MCLK

There is a direction bit of SAI1_MCLK( SAI1_MCLK_DIR) , which can be found in i.MX6UL reference mauanl. The bit should be set to 1,then SAI1_MCLK will output.

Try above suggestions, please!

Have a nice day!

NXP TIC Weidong

hitesh_kasera · ‎04-17-2019

Hi Wigros,

i have modified in my probe function to set direction of SAI_MCLK. I have measured SAI_MCLK its around 44.4 Mhz still not set to 12.288 Mhz. This is how my probe function looks. Still i am getting same 11 Mhz clock bclk for sampling rate 48000.

static int imx_sph0645_probe(struct platform_device *pdev)
{
   struct snd_soc_card *card = &snd_soc_card_imx_3stack;
   struct device_node *cpu_np, *np = pdev->dev.of_node;
   struct platform_device *cpu_pdev;
   struct regmap *gpr;
   int ret;

   cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0);
   if (!cpu_np) {
       dev_err(&pdev->dev, "phandle missing or invalid\n");
       return -EINVAL;
   }

   cpu_pdev = of_find_device_by_node(cpu_np);
   if (!cpu_pdev) {
       dev_err(&pdev->dev, "failed to find SAI platform device\n");
       ret = -EINVAL;
       goto end;
   }

   gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
           if (IS_ERR(gpr)) {
               dev_err(&pdev->dev, "cannot find iomuxc registers\n");
               return PTR_ERR(gpr);
               }
   regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(1),MCLK_DIR(1));

   card->dev = &pdev->dev;
   card->dai_link->cpu_dai_name = dev_name(&cpu_pdev->dev);
   card->dai_link->platform_of_node = cpu_np;

platform_set_drvdata(pdev, card);

   ret = snd_soc_register_card(card);
   if (ret)
       dev_err(&pdev->dev, "Failed to register card: %d\n", ret);

end:
if (cpu_np)
of_node_put(cpu_np);

return ret;
}

I have also attached driver file for your reference.

Thanks & Regards,

Hitesh

weidong_sun · ‎04-17-2019

Hello Hitesh,

The issue on SAI1_MCLK output seems to be caused by clock parent.

&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>; // you should ensure PAD's multiplexing is correct.

assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
<&clks IMX6UL_CLK_SAI1>;

   assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; // parent should be set before rate.
    assigned-clock-rates = <0>, <12288000>; //IMX6UL_CLK_SAI1_SEL=0, IMX6UL_CLK_SAI1=12.288MHz
    fsl,sai-mclk-direction-output; // sai driver will set the bit.

status = "okay";
};

I saw you had configured gpr1 register in your machine driver, you can dump the value of register after line:

"regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(1),MCLK_DIR(1));"

Try it please!

We shoud firstly let SAI1_MCLK pin's output is correct (12.288MHz)

Have a nice day!

Weidong

hitesh_kasera · ‎04-17-2019

HI wigros,

I have tried what you have said. here is my new device tree :

&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;

    /*
     * Reference block.
     *
     * Codec dependent section.
     */
    assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
            <&clks IMX6UL_CLK_SAI1>;
    assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <0>, <12288000>;
    fsl,sai-mclk-direction-output;

status = "okay";
};

and imx6ul.dtsi is : (didnt modify)

                sai1: sai@02028000 {
                   #sound-dai-cells = <0>;
                   compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
                   reg = <0x02028000 0x4000>;
                   interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                   clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
                       <&clks IMX6UL_CLK_DUMMY>,
                       <&clks IMX6UL_CLK_SAI1>,
                       <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
                   clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
                   dmas = <&sdma 35 24 0>,
                           <&sdma 36 24 0>;
                   dma-names = "rx", "tx";
                   status = "disabled";
               };

still i am getting sai_mclk around 44.4 Mhz. i didnt get what you said about gpr

"you can dump the value of register after line:

"regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(1),MCLK_DIR(1));""

i have already in driver has set the bit as you have seen.

what am i missing?

Thanks & Regards,

Hitesh

weidong_sun · ‎04-18-2019

Hello Hitesh,

Please see the link!

Same solution as yours!

https://community.nxp.com/message/1132564?commentID=1132564#comment-1132564

Hope it can help you!

Have a nice day!

Weidong

hitesh_kasera · ‎04-18-2019

Hi wigros,

i have already seen that has ssi instead of sai. i have discussed with jarrod too. as i have shared with you in fsl sai it prints out master clock 12.288Mhz. what might be the reason for getting 44.4Mhz master clock?. This is the clock summary i have got while running command

cat /sys/kernel/debug/clk/clk_summary

I have bolded the sai 1 clock.

clock                         enable_cnt prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
dummy                                    3            3           0          0 0
    usbphy2_gate                          1            1           0          0 0
    usbphy1_gate                          1            1           0          0 0
ipp_di1                                  0            0           0          0 0
ipp_di0                                  0            0           0          0 0
    pll4                                  0            0   147456000          0 0
       pll4_bypass                        0            0   147456000          0 0
          pll4_audio                      0            0   147456000          0 0
             pll4_post_div                0            0    36864000          0 0
                pll4_audio_div            0            0    36864000          0 0
                   sai1_sel               0            0    36864000          0 0
                      sai1_pred           0            0    12288000          0 0
                         sai1_podf           0            0    12288000          0 0
                            sai1           0            0    12288000          0 0

    pll2                                  1            1   528000000          0 0
       pll2_bypass                        1            1   528000000          0 0
          pll2_bus                        3            3   528000000          0 0
             periph_pre                   1            1   528000000          0 0
                periph                    2            2   528000000          0 0
                   ahb                    8            9   132000000          0 0
                      sdma                4            2   132000000          0 0
                      rom                 1            1   132000000          0 0
                      enet_ahb            0            0   132000000          0 0
                      aips_tz3            1            1   132000000          0 0
                      caam_aclk           2            2   132000000          0 0
                      caam_mem            2            2   132000000          0 0
                      asrc_mem            0            0   132000000          0 0
                      asrc_ipg            0            1   132000000          0 0
                      aips_tz2            1            1   132000000          0 0
                      aips_tz1            1            1   132000000          0 0
                      ipg                 4            5    66000000          0 0
                         wdog3            0            0    66000000          0 0
                         uart8_ipg           0            0    66000000          0 0
                         usboh3           0            0    66000000          0 0
                         sai2_ipg           0            0    66000000          0 0
                         sai1_ipg           0            1    66000000          0 0
                         uart7_ipg           0            0    66000000          0 0
                         uart1_ipg           1            1    66000000          0 0
                         sai3_ipg           0            0    66000000          0 0
                         spdif_gclk           0            0    66000000          0 0
                         spba             0            0    66000000          0 0
                         wdog2            0            0    66000000          0 0
                         kpp              0            0    66000000          0 0
                         mmdc_p0_ipg           1            1    66000000          0 0
                         wdog1            0            0    66000000          0 0
                         uart6_ipg           0            0    66000000          0 0
                         enet             0            0    66000000          0 0
                         uart5_ipg           1            2    66000000          0 0
                         ocotp            0            0    66000000          0 0
                         uart4_ipg           0            0    66000000          0 0
                         adc1             0            0    66000000          0 0
                         uart3_ipg           0            0    66000000          0 0
                         adc2             0            0    66000000          0 0
                         uart2_ipg           0            0    66000000          0 0
                         can2_ipg           0            0    66000000          0 0
                         can1_ipg           0            0    66000000          0 0
                         caam_ipg           2            2    66000000          0 0

Thanks & Regards,

Hitesh

weidong_sun · ‎04-18-2019

Hello Hitesh,

Could you show me the multiplexing pins of SAI1 you are using?

it will be better to show it to me in dts file.

Have a nice day!

Weidong

hitesh_kasera · ‎04-18-2019

Hi wigros,

This is how sai looks in dts file.

pinctrl_sai1: sai1grp {
            fsl,pins = <
                MX6UL_PAD_LCD_DATA00__SAI1_MCLK       0x17088
                MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA       0x11088
                MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK       0x17088
                MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA       0x11088
                MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC       0x17088
            >;
        };

i am using only 3 pins in hardware sai1tx_bclk, sai1_tx_sync and sai1_rx_data. I have also attached .dts file in which i have define sai1.

Let me know if you need any more information.

Thanks & Regards,

Hitesh

weidong_sun · ‎04-19-2019

OK, got it. I will take some time to check them.

Have a nice day!

BR,

Weidong

hitesh_kasera · ‎04-19-2019

Hi wigros,

Thanks a lot for your help. let me know your findings.

Have a nice weekend!

Regards,

Hitesh

weidong_sun · ‎04-21-2019

Dear Hithesh,

I found in your dts file, LCD port has been used:

        pinctrl_lcdif_dat0_17: lcdifdatgrp0_17 {
           fsl,pins = <
               MX6UL_PAD_LCD_DATA00__LCDIF_DATA00   0x79
               MX6UL_PAD_LCD_DATA01__LCDIF_DATA01   0x79
               MX6UL_PAD_LCD_DATA02__LCDIF_DATA02   0x79
               MX6UL_PAD_LCD_DATA03__LCDIF_DATA03   0x79
               MX6UL_PAD_LCD_DATA04__LCDIF_DATA04   0x79
               MX6UL_PAD_LCD_DATA05__LCDIF_DATA05   0x79
               MX6UL_PAD_LCD_DATA06__LCDIF_DATA06   0x79
               MX6UL_PAD_LCD_DATA07__LCDIF_DATA07   0x79
               MX6UL_PAD_LCD_DATA08__LCDIF_DATA08   0x79
               MX6UL_PAD_LCD_DATA09__LCDIF_DATA09   0x79
               MX6UL_PAD_LCD_DATA10__LCDIF_DATA10   0x79
               MX6UL_PAD_LCD_DATA11__LCDIF_DATA11   0x79
               MX6UL_PAD_LCD_DATA12__LCDIF_DATA12   0x79
               MX6UL_PAD_LCD_DATA13__LCDIF_DATA13   0x79
               MX6UL_PAD_LCD_DATA14__LCDIF_DATA14   0x79
               MX6UL_PAD_LCD_DATA15__LCDIF_DATA15   0x79
               MX6UL_PAD_LCD_DATA16__LCDIF_DATA16   0x79
               MX6UL_PAD_LCD_DATA17__LCDIF_DATA17   0x79
           >;
       };

LCD_DATA00 PAD has been multiplexed as LCD_DATA00,

and here it was used to be SAI1_MCLK:

pinctrl_sai1: sai1grp {
            fsl,pins = <
                MX6UL_PAD_LCD_DATA00__SAI1_MCLK       0x17088
                MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA       0x11088
                MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK       0x17088
                MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA       0x11088
                MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC       0x17088
            >;
        };

So there exists multiplexing conflict.

Check it , please!

Have a nice day!

Best Regards,

NXP TIC Weidong

hitesh_kasera · ‎04-25-2019

Hi Wigros,

i have commented lcdif data pins but still i am getting the same SAI MCLK clock around 44.4Mhz. i have also attached final .dts file which i generated from .dtb files contained in images folder.

Let me know your inputs.

Thanks & Regards,

Hitesh

weidong_sun · ‎04-25-2019

Dear Hitesh,

I will spend some time check these files.

Have a nice day!

BR,

Weidong

weidong_sun · ‎04-27-2019

Dear Hitesh,

I found the these dts files are for SOC , actually, The configurations for those IPs in SOC are defined in *.dtsi, which doesn't need to be modified. If you modify or rename it, unpredictable errors may occur.

You only need to include .dtsi in your own dts file for your board.

In addition, I reviewed what we discussed before, see the source code:

and imx6ul.dtsi is : (didnt modify)

                sai1: sai@02028000 {
                   #sound-dai-cells = <0>;
                   compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
                   reg = <0x02028000 0x4000>;
                   interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                   clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
                       <&clks IMX6UL_CLK_DUMMY>,
                       <&clks IMX6UL_CLK_SAI1>,
                       <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
                   clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
                   dmas = <&sdma 35 24 0>,
                           <&sdma 36 24 0>;
                   dma-names = "rx", "tx";
                   status = "disabled";
               };

It seems here should be "status = "okay";", otherwise, SAI1 driver can't be enabled.

Try it , please!

Have a nice day!

Weidong

hitesh_kasera · ‎04-29-2019

Hi Wigros,

Thank you for your inputs.

i have tried modifying as you said in imx6ul.dtsi but still my master clock is around 44 Mhz. To update any component in device tree file i modify one of the files imx6ul-ccimx6ulsbc.dtsi, imx6ul-ccimx6ulsbc-id135.dts, imx6ul-ccimc6ulsbc-wb.dts. for 44 Mhz master clock i am getting around 11 Mhz, divison factor here is 4. according to what i parse the master clock 12.288 Mhz and for 48000 sampling rate (bit clock = 3.072Mh) division should be 4 so fsl_sai.c code calculating division according to parse parameters. Also i am able to get frame sync clock bit clock/64. The only thing is its not providing parsed master clock as for 48Khz it should be 12.288Mhz as you also said .

Let me know what you think should be changed or you require any other inputs from my side.

Thanks & Regards,

Hitesh

weidong_sun · ‎04-29-2019

Dear Hitesh,

I have submitted the question to i.MX Expert team, Let us ask for help from expert team, and wait for their reply.

Have a nice day!

BR,

Weidong

hitesh_kasera · ‎05-02-2019

Hi Wigros,

Thanks a lot for speaking with expert team. let me know their inputs.

Regards,

Hitesh

weidong_sun · ‎05-04-2019

Dear Hitesh,

i.MX Expert gave us feedback, try it please!

----------------------------------

1.

For the below call, 2nd param should be mclk_id, looks like you should pass "1":

ret = snd_soc_dai_set_sysclk(cpu_dai, 0, bclk, SND_SOC_CLOCK_OUT);

Please debug into the fsl_sai_set_dai_sysclk() for the clock configurations and generations.

2.

Also, you should not set the cpu dai sysclk in the code driver. Please refer to the imx-wm8960.c.

------------------------------------

Have a nice day!

BR,

weidong

hitesh_kasera · ‎05-05-2019

Hi Wigros,

i have already done that ret = snd_soc_dai_set_sysclk(cpu_dai, 1, bclk, SND_SOC_CLOCK_OUT) but still i am getting same around 44.4 Mhz Master Clock Bit Clock - 11.1Mhz if i pass sampling rate 48000. as you said about system clock function not to pass frequency i dont see any use of this frequency in function fsl_sai_set_dai_sysclk(). it is not used in this function. I also tried to debug the fsl_sai.c script i have attached where i added print in that file and all looks ok there. when i run the below command the output i have added here what i got:

Command : arecord -c 2 -d 5 -f S32 -r 16000 -v /home/root/test.wav

Recording WAVE '/home/root/test.wav' : Signed 32 bit Little Endiafsl-sai 2028000.sai: sampling rate parms_rate output rate : 16000
n, Rate 16000 Hz, Stereo
fsl-sai 2028000.sai: bclk : 1024000
fsl-sai 2028000.sai: Entered into fsl sai set dai tdm slot:
fsl-sai 2028000.sai: Entered into fsl sai set dai sys clk:
fsl-sai 2028000.sai: Entered into fsl sai set dai sys clk tr: tx : 1
fsl-sai 2028000.sai: Entered into fsl sai set dai sys clk tr: tx : 0
fsl-sai 2028000.sai: Entered into fsl sai hw params:
fsl-sai 2028000.sai: Entered into fsl sai hw params slots: 2
fsl-sai 2028000.sai: Entered into fsl sai hw params slot_width: 32
fsl-sai 2028000.sai: Entered into fsl sai hw params sampling_rate: 16000
fsl-sai 2028000.sai: Entered into fsl sai set bclk with freq: 1024000 Hz
fsl-sai 2028000.sai: Entered into fsl sai set bclk mclk_clk[0] = 0Hz:
fsl-sai 2028000.sai: Entered into fsl sai set bclk mclk_clk[1] = 12288000Hz:
fsl-sai 2028000.sai: Entered into fsl sai set bclk ratio = 12:
fsl-sai 2028000.sai: Entered into fsl sai set bclk id and tx : 0, id = 1:
, savediv :6
fsl-sai 2028000.sai: Entered into fsl sai set bclk asynchronous:
fsl-sai 2028000.sai: Entered into fsl sai hw params exited from set bclk: ret = 0
fsl-sai 2028000.sai: Entered into fsl sai hw params exited from bclk: sai->mclkstreams = 0 , BIt:2, mclk_clk :12288000 , tx: 0
fsl-sai 2028000.sai: Entered into fsl sai hw params exited from bclk: sai->mclkstreams = 2
Plug PCM: Hardware PCM card 0 'imx-audio-sph0645' device 0 subdevice 0
Its setup is:
stream       : CAPTURE
access       : RW_INTERLEAVED
format       : S32_LE
subformat    : STD
channels     : 2
rate         : 1600fsl-sai 2028000.sai: Entered into fsl sai trigger:
0
exact rate   : 16000 (16000/1)
msbits       : 32
buffer_size : 8000
period_size : 2000
period_time : 125000
tstamp_mode : NONE
tstamp_type : MONOTONIC
period_step : 1
avail_min    : 2000
period_event : 0
start_threshold : 1
stop_threshold   : 8000
silence_threshold: 0
silence_size : 0
boundary     : 2097152000
appl_ptr     : 0
hw_ptr       : 0
fsl-sai 2028000.sai: Entered into fsl sai trigger:
fsl-sai 2028000.sai: Entered into fsl sai shutdown:

Let me Know your inputs.

Thanks & Regards,

Hitesh

weidong_sun · ‎05-07-2019

Dear Hitesh,

Just now I tried to use dummy codec on i.MX6UL 14X14 EVK board, when I was modifying configurations in imx6ul-14x14-evk.dts, I found "gpr" should be changed to be "gpr = <&gpr 4 0x80000 0x80000>;", which means the bit19(SAI1_MCLK_DIR) of IOMUX_GPR_GPR1 should be set to 1, and "4" means the register's offset is "4h".

So please check your configurations in dts!

Then try it, please!

Have a nice day!

BR,

Weidong

I2S microphone (SPH0645LM4H) Driver Implementation with i.mx6ul

I2S microphone (SPH0645LM4H) Driver Implementation with i.mx6ul

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