Hello,
I'm using a kernel 3.10.17_1.0.0_ga.
My codec is a WM8740 and must be driven by an external clock. IMX can provide this oversampling clock with I2S master mode and SYS_CLK_EN=1.
I'm facing an issue with the fsl_ssi_set_dai_sysclk in fsl_ssi.c which is not calculating correctly the sys clock according to the bitclock requested.
When asking 2822400 which is 44100 * 2 * 32, the sys clock which is calculated is too high(79Mhz instead of 11.2896MHz) as PM (13) for common use of codec such as WM8740.
So i wrote a patch to fix this issue and get acceptable sysc clock.
But concerning higgh frequency such as 192kHz, we are not able to respect this comment as I disabled the check part in the patch.
The bclk rate must be smaller than 1/5 sysclk rate */
So I would like to confirm first the patch i applied to fsl_ssi.c and understand why this comment in the code and in the IMX6Q's documentation.
rgds.
Stephane
Hi Cerveau
this restriction is from IMX6DQRM sect.61.8.4 SSI Clocking
Best regards
igor
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Hello Igor,
Thank you for your answer.
I still dont anwser why its forbidden to have a bitclock greater than 1/5 of the ipg_clk. I have read this caution in documentation.
In my case, in order to get a working 192kHz sample rate, i need 24.576MHz or 36.384MHz (WM8740 Table) as sys clock and 32 *2 * 192000=12,288MHz as bitclock.
So in this case, ipg_clock=24.576MHz and pm=0.
I have been working like this for about a year with previous kernel 3.0.35 without any issues.
Please let me know about the consequences if there are ?
Stephane
Hi Cerveau
this is forbidden due to processor harwdare design,
that is internal SSI module synchronization is guaranteed provided that
that requirement is fulfiled.
~igor
Hi,
I'm not sure to catch you.
Why is it possible to do it software speaking, can it damage the hardware (??)?
Is there some potential jitter issue ?
In my case how can I generate a 192kHz sample rate setup so ?
Best regards.
Stéphane
SSI hadrware forbids to have a bitclock greater than 1/5 of the ipg_clk.
This is described in RM.
Hey Igor,
I read it in the RM too.
I'm sorry to insist but what are the consequences if i dont take this limitation into account?
In table 61.7 in IMX6QDRM.pdf, there is this line where pm is equal to 1 and so bitclk/ssi_sys_clk is equal 1/4 so greater than 1/5
Thx in advance for your support
Hi Cerveau
consequences may be that is some
corner PVT cases it may work unpredictable.
table/software comments may be inaccurate, since these
may be left from previous processors docs.
Best regards
igor