Hi
We are using a Variscite DART-6UL SOM (MCIMX6G2 proc) placed on a custom board. As build environment buildroot is used. The SOM has one PHY (KSZ8081) populated on the first ethernet lines. This is the ethernet line we use, balls belonging to 2nd ethernet controller are used as uarts, digital io's, chip select signals and so on.
We ran into troubles with radiated emission measurements, seeing spike @ 200 and 300 MHz exceeding the limits by far (over 10dB). We did following investigations:
Is there a way to stop this coupling out by software? For now we only "disabled" fec2 in the device tree. Are there way's to stop that more explicitly, or at least to lower the harmonics going out? The Variscite support seems also be reaching its limit, so any advise, input or suggestion is highly appreciated
Thanks in advance
Louis
Hi Louis
seems most simple is to disable enet clock using CCM_CCGR3(CG2) register.
With software changes for fec2 one can try to change IOMUXC_GPR_GPR1 (ENET2_CLK_SEL,ENET2_TX_CLK_DIR).
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hi Igor
thanks a lot for your response. I changed the settings with devmem on GPR1 register. It turned out that the noise isn't coming from fec2, but is coupling out from ENET1_TX_CLK. By setting the IOMUX pad to a higher output resistance we can reduce emissions by about 15dB, with even not too ugly clock signal. I'll check with the SOM support for correct solution.
Best regards
Louis