From the i.MX 8M Plus Application Processor Reference Manual
5.3.2 Functional Description
The 24MHz oscillator will be used as the primary clock source for the PLLs to generate
the clock for CPU, BUS, and high-speed interfaces. For all PLLs, the 24MHz clock from
the oscillator can be used as the PLL reference clock directly.
The OSC IP used by the 24MHz XTAL module has three modes, Internal clock
generation mode, External clock receive mode and Retention mode.
During internal clock generation mode, a suitable quartz crystal is connected between
PADI and PADO to generate the clock signal at the CK pin.
During external clock generation mode, the cell acts like a buffer, reflecting the PADI
signal at CK.
The RTO (retention enable) signal retains the previous state of all the core input control
signals. Logic at the RTO signal enables the retention operation.
Each XTAL module supports the following modes through register configuration:
• Normal oscillator mode - In normal mode, the XTAL IP generates stable square
wave based on the crystal oscillator input.
• Bypass mode - In bypass mode, an external clock can be input through the XTAL
pad.
Does it means can use external clock generator ?
