We are using LDM/STM instruction(shown below) to transfer data from i.mx6 over SRAM interface but the performance is same as no LDM/STM.
asm(
"pld [%[address]]\n\t"
"vldm %[address],{q0-q7}\n\t"
"vstm %[address1]!,{q0-q7}\n\t"
://outputs
:[address]"r"(array),[address1]"r"(pusAddr16)//inputs
:"q0","q1","q2","q3","memory"//clobbers
);
Everyone says that cache should be enabled to achieve high performance using STM/LDM.
I am new to freescale and can someone guide me How to enable cache for i.mx6 EIM?
Thanks and Regards,
Rinkesh Patel
Hi Rinkesh
in linux caches are already enabled, as for example code
one can look at ..sdk/core/src/armv7_cache.c
i.MX 6Series Platform SDK : Bare-metal SDK
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hello Igore,
Thank you very much for your reply.
Regards,
Rinkesh Patel