How to change clko_clk to 16.9344MHZ as I2S mclk in the IMX6 and the kernel version is 3.0.35?

[fdact]

Dear Sir or Madam,

            We use imx6Q as I2S master, we find the mclk can't be set to less than 24MHZ,but we need mckl and ssi1_clk

can be set to less than 24MHZ. Please give me some advice.

Thanks.

[fdact]

Hi,

Thanks for your reply. I have two doubts, the first one is :

I already set ssi1_clk parent is pll4, and according to the code can calculate the minimum frequency of SSI is 20.3125MHZ (ps:650/4/8),

But why is the value of the minimum set of SSI is 24MHZ that I already set pll4 to 162.5MHZ?  MCLK also has the same problem.

the second is  I need to make the I2S output meet the following conditions:

1. mclk = 384*LRCK or 512 *LRCK

2.sclk = 2 * sample_rate *channels

I will try to your advice" try to set pll bypass and use 24MHz as pll output",

In order to be able to set a smaller frequency, I will set their parent  to 24MHZ,

But I think this set the precision of a lot of it, because it is the integer division?

Please give me some advice.

Thanks.

[igorpadykov]

Hi zhao

one can try to set pll bypass and use 24MHz as pll output or select pll input

from CLK_N / CLK_P externally, please check sect.18.7.8 Analog Audio PLL

control Register (CCM_ANALOG_PLL_AUDIOn) i.MX6DQ RM.

Best regards

igor

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[fdact]

Hi,

Thanks for your reply. I have two doubts, the first one is :

I already set  clko_clk parent is pll4, and according to the code can calculate the minimum frequency of SSI is 20.3125MHZ (ps:650/4/8),

But why is the value of the minimum set of clko_clk is 24MHZ that I already set pll4 to 162.5MHZ?  ssi1_clk also has the same problem.

the second is  I need to make the I2S output meet the following conditions:

1. mclk = 384*LRCK or 512 *LRCK

2.sclk = 2 * sample_rate *channels

I will try to your advice" try to set pll bypass and use 24MHz as pll output",

In order to be able to set a smaller frequency, I will set their parent  to 24MHZ,

But I think this set the precision of a lot of it, because it is the integer division?

Please give me some advice.

Thanks.

[igorpadykov]

what do you mean by :

"But why is the value of the minimum set of clko_clk is 24MHZ that I already set pll4 to 162.5MHZ? "

could you clarify?

>But I think this set the precision of a lot of it, because it is the integer division?

what do you mean by 'precision" ?

[fdact]

Hi,

Part of the code is as follows:

1.static struct clk ssi1_clk = {

    __INIT_CLK_DEBUG(ssi1_clk)

     .parent = &pll4_audio_main_clk,

2.clk_set_rate(&pll4_audio_main_clk, 162500000);

3. rate = clk_round_rate(card_priv.ssi_clk, 22579200);

The return value of rate is 24000000. That I said "But why is the value of the minimum set of ssi1_clk  is 24MHZ that I already set pll4 to 162.5MHZ?" problem。

what do you mean by 'precision" ?

      If I set parent clock of ssi1_clk  to 24MHZ, how to modify ssi1_clk value to 22579200HZ or 16934400HZ?

Thanks.

[igorpadykov]

>  If I set parent clock of ssi1_clk  to 24MHZ, how to modify ssi1_clk value to 22579200HZ or 16934400HZ?

you should use appropriate pll value or probably change 24MHz crystal

to another value.

[fdact]

Hi,

    Like I said above , According to the calculation clk can reach the value if I set pll to 162.5MHZ . The problem is  the ssi_clk can't less than 24MHZ not matter how to change PLL value and SSI1 clk value !  

Thanks.

[igorpadykov]

in such case suggest to use external reference clock

with suitable frequency connected CLK1_N / CLK1_P as

pll source and (probably) use pll bypass.

[fdact]

Hi,

    Look at the specifications IMX 6QD RM  can be achieve  our requirement, you know the cause of the problem for me?

    And can you tell me how to use pll bypass,have you any examples of code ,I want try it .

Thanks.