I keep getting a delay of 20us - 50us, when the SS is set low, to the clock and data transfer begins on the SPI ports on the imx6ul. I run a linux system on the chip with kernel version 4.9. There does not seem to be any correlation between the frequency and and the delay. Is there somewhere in the SPI driver, that I can change the parameter so this does not happen?
See pictures for clarification, the blue is the SS pin, the yellow is CLK and purple is MOSI.
Best regards,
Anders
Hi Anders
one can try patch changing "gpio" spi chip selects to spi native chip selects
kernel/git/next/linux-next.git - The linux-next integration testing tree
Best regards
igor
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Hi Igor
The patch could not implement the 3rd change, I don't know if I missed something, I use Yocto to build the system, and just added the .diff file to my kernel.bbappend file.
I tried the 2 first changes but that did not seem to do anything to the timing from SS to CLK signal.
Best regards,
Anders